The following examples infer a D-latch with gated enable.Figure 11-11. D-Latch with Gated
Enable
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity d_latch_en is
port (enable, gate, d: in std_logic;
q : out std_logic);
end d_latch_en;
architecture behave of d_latch_en is
begin
process (enable, gate, d) begin
if ((enable and gate) = '1') then
q <= d;
end if;
end process;
end behave;
Verilog
module d_latch_en(enable, gate, d, q);
input enable, gate, d;
output q;
reg q;
always @ (enable or d or gate)
if (enable & gate)
q = d;
endmodule
