11.2.1.1 Flip-Flops (Registers)

Flip-flops, also called registers, are inferred in VHDL using wait and if statements within a process using either a rising edge or falling edge detection expression. There are two types of expressions that can be used, a 'event attribute or a function call. For example:

(clk'event and clk='1') --rising edge 'event attribute
(clk'event and clk='0') --falling edge 'event attribute
rising_edge(clock) --rising edge function call
falling_edge(clock) --falling edge function call

The examples in this guide use rising edge 'event attribute expressions, but falling edge expressions could be used. The 'event attribute expression is used because some VHDL synthesis tools may not recognize function call expressions. However, using a function call expression is preferred for simulation because a function call only detects an edge transition (0 to 1 or 1 to 0) but not a transition from X to 1 or 0 to X, which may not be a valid transition. This is especially true if using a multi-valued data type like std_logic, which has nine possible values (U, X, 0, 1, Z, W, L, H, -). This section describes and gives examples for different types of flip-flops. Refer to “Registers” for additional information about using specific registers in the Microchip architecture.