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Libero IDE v9.x
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5
Libero IDE
5.30
Running Layout
5.30.2
IGLOO, ProASIC3, SmartFusion and Fusion Advanced Layout Options
5.30.2.3
Router
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
5.1
What's New in Libero IDE v9.1
5.2
Supported Families
5.3
Project Management
5.4
Project Files
5.5
Project Options
5.6
Settings
5.7
Preferences
5.8
Project Manager Interface
5.9
Designing with Designer Block Components
5.10
Creating a Designer Block Component in Libero IDE
5.11
Creating a Designer Block Component in Designer
5.12
Instantiating a Designer Block Component in Designer
5.13
SmartDesign
5.14
Getting Started with SmartDesign
5.15
SmartDesign User Interface
5.16
Canvas View
5.17
Grid
5.18
Instance-Instance View
5.19
Schematic View
5.20
Creating a SmartDesign
5.21
Connecting Instances
5.22
Bus Interfaces
5.23
Incremental Design
5.24
Reference
5.25
Welcome to Designer
5.26
Device Selection
5.27
Design Constraints
5.28
Families Supported
5.29
Entering Constraints
5.30
Running Layout
5.30.1
IGLOO, ProASIC3, SmartFusion and Fusion Layout Options
5.30.2
IGLOO, ProASIC3, SmartFusion and Fusion Advanced Layout Options
5.30.2.1
High Effort Layout Mode
5.30.2.2
Sequential Optimization
5.30.2.3
Router
5.30.2.3.1
Repair Minimum Delay Violations
5.30.2.3.2
Additional Factors
5.30.2.4
Restore Defaults
5.30.3
ProASIC PLUS and ProASIC Layout Options
5.30.4
ProASIC PLUS and ProASIC Advanced Layout Options
5.30.5
Axcelerator Layout Options
5.30.6
Axcelerator Advanced Layout Options
5.30.7
eX, SX, SX-A Layout Options
5.30.8
eX, SX, and SX-A Advanced Layout Options
5.30.9
ACT, MX, and DX Layout Options
5.30.10
ACT, MX, and DX Advanced Layout Options
5.30.11
Incremental Placement
5.30.12
Running Multiple Pass Layout
5.30.13
Analyzing timing in your design
5.30.14
Analyzing power consumption in your design
5.30.15
Viewing your netlist
5.30.16
Back-Annotation
5.30.17
Report types
5.30.18
Status Reports
5.30.19
Generating a Timing Report
5.30.20
Generating a Timing Violation Report
5.30.21
Generating a Bottleneck Report
5.30.22
Generating a Datasheet Report
5.30.23
Generating a Constraints Coverage Report
5.30.24
Generating a Combinational Loop Report
5.30.25
Pin reports
5.30.26
Flip-flop reports
5.30.27
I/O Bank Reports
5.30.28
Power Reports
5.30.29
Cycle-Accurate Power Reports
5.30.30
Activity and Hazards Reports
5.30.31
Scenario Power Report
5.30.32
CCC Configuration report
5.30.33
report (Global Usage)
5.30.34
Global Usage report
5.30.35
Designer Block Report
5.30.36
Compile report
5.31
Device Programming
5.32
Generating Programming Files
5.33
TCL Command Reference
5.34
Project Manager Tcl Commands
5.35
Reference
5.36
Dialog Boxes
5.37
Revision History
5
Microchip FPGA Support
5
Microchip Information
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
5.30.2.3 Router
Rev: A
