14.1.2 How to Use this Guide

Family Inclusion Indicator

In the titlebar of each macro is a list indicating whether the cell is a member of the ACT 1, ACT 2, 3200DX, ACT 3, MX, SX, SX-A, eX, or Axcelerator library.

Guidelines

  1. All input pin loading is assumed to be a single load except macros that are built using two combinational modules or one sequential and one combinatorial module. These macros are assumed to have a load of two on some of their input pins.
  2. All macros have output pin loading of zero except for the sequential macros that are built using two combinational modules only. These macros have an output pin loading of one.
  3. All macros have logic levels equal to one except cells with pin delays of two. A “2” is added to the corresponding symbol in the macro section of this manual.

Truth Table Nomenclature

Truth tables are arranged with Inputs before Outputs. The following symbol definitions apply

↑ denotes rising edge clock

↓ denotes falling edge clock

X in an input column denotes a ‘don't care’ or logic simulation state ‘unknown

!Q denotes Q not

Pin Delay Annotation

Two-module combinatorial macros contain extra delay on some or all of the pins. If a macro symbol in this guide displays a “2” on a pin, then two levels of logic delay exist on the input to output path.

Note: Many two-level logic functions in one family are implemented in a single module in another family, hence the “2” may apply to specific families only.