5.24.19.1 Identify features:

• Instrument and debug your FPGA directly from RTL source code .
• Internal design visibility at full speed.
  • Incremental iteration - Design changes are made to the device from the Identify environment using incremental compile. You iterate in a fraction of the time it takes route the entire device.
• Debug and display results - You gather only the data you need using unique and complex triggering mechanisms.

You must have both the Identify RTL Debugger and the Identify Instrumentor to run the debugging flow outlined below.

To use the Identify debugger:

1. Create your source file (as usual) and run pre-synthesis simulation.
2. (Optional) Run through an entire flow (Synthesis - Designer - FlashPro) without starting Identify.
   1. Click the Synthesis Synplify button in the Libero IDE to launch Synplify. From within Synplify, launch the Identify Instrumentor.
   2. From the Instumentor UI specify the sample clock, the breakpoints, and other signals to probe. Synplify creates a new synthesis implementation. Synthesize the design.
3. In Libero IDE, select the edif netlist of the Identify implementation you want to use in the flow.
4. Run Designer and FlashPro with the edif netlist you created with the Identify implementation.
5. Click the Debugging button in the Design Flow window to launch the Identify Debugger.

The Identify RTL Debugger, Synplify, and FlashPro must be synchronized in order to work properly. See the Release Notes for more information on which versions of the tools work together.