38.13.24 CxFIFOCONy
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxFIFOCONyT: Accesses the top byte FIFOCONy[31:24]
- CxFIFOCONyU: Accesses the upper byte FIFOCONy[23:16]
- CxFIFOCONyH: Accesses the high byte FIFOCONy[15:8]
- CxFIFOCONyL: Accesses the low byte FIFOCONy[7:0]
- [y] denotes FIFO number, from 1 to 3.
- These bits can only be
modified in Configuration mode (OPMOD[2:0] =
100
).
Name: | CxFIFOCONy |
Offset: | 0x00 |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PLSIZE[2:0] | FSIZE[4:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TXAT[1:0] | TXPRI[4:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FRESET | TXREQ | UINC | |||||||
Access | S/HC | R/W/HC | S/HC | ||||||
Reset | 1 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TXEN | RTREN | RXTSEN | TXATIE | RXOVIE | TFERFFIE | TFHRFHIE | TFNRFNIE | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:29 – PLSIZE[2:0] Payload Size(3)
Value | Description |
---|---|
111 | 64 data bytes |
110 | 48 data bytes |
101 | 32 data bytes |
100 | 24 data bytes |
011 | 20 data bytes |
010 | 16 data bytes |
001 | 12 data bytes |
000 | 8 data bytes |
Bits 28:24 – FSIZE[4:0] FIFO Size(3)
Bits 22:21 – TXAT[1:0] Retransmission Attempts
Value | Description |
---|---|
11 | Unlimited number of retransmission attempts |
10 | Unlimited number of retransmission attempts |
01 | Three retransmission attempts |
00 | Disables retransmission attempts |
Bits 20:16 – TXPRI[4:0] Message Transmit Priority
Value | Description |
---|---|
11111 | Highest message priority |
00000 | Lowest message priority |
Bit 10 – FRESET FIFO Reset
Value | Description |
---|---|
1 | FIFO will be reset when bit is set, cleared by hardware whenever FIFO is reset, user needs to poll whether this bit is clear before taking any action |
0 | No effect |
Bit 9 – TXREQ Message Send Request
Value | Name | Description |
---|---|---|
1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent |
0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Clearing the bit to ‘0 ’ while set (‘1 ’)
will request a message abort |
x | TXEN = 0 (FIFO configured as a receive
FIFO) |
This bit has no effect |
Bit 8 – UINC Increment Head/Tail
Value | Name | Description |
---|---|---|
1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
When this bit is set, the FIFO head will increment by a single message |
1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
When this bit is set, the FIFO tail will increment by a single message |
Bit 7 – TXEN TX/RX Buffer Selection
Value | Description |
---|---|
1 | Transmits message object |
0 | Receives message object |
Bit 6 – RTREN Auto-Remove Transmit (RTR) Enable
Value | Description |
---|---|
1 | When a Remote Transmit is received, TXREQ will be set |
0 | When a Remote Transmit is received, TXREQ will be unaffected |
Bit 5 – RXTSEN Received Message Timestamp Enable(3)
Value | Description |
---|---|
1 | Captures timestamp in a received message object in RAM |
0 | Does not capture time stamp |
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable
Value | Description |
---|---|
1 | Enables interrupt |
0 | Disables interrupt |
Bit 3 – RXOVIE Overflow Interrupt Enable
Value | Description |
---|---|
1 | Interrupt is enabled for overflow event |
0 | Interrupt is disabled for overflow event |
Bit 2 – TFERFFIE Transmit/Receive FIFO Empty/Full Interrupt Enable
Value | Name | Description |
---|---|---|
1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO empty |
0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO empty |
1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO full |
0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO full |
Bit 1 – TFHRFHIE Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable
Value | Name | Description |
---|---|---|
1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO half empty |
0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO half empty |
1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO half full |
0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO half full |
Bit 0 – TFNRFNIE Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable
Value | Name | Description |
---|---|---|
1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO not full |
0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO not full |
1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO not empty |
0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO not empty |