38.13.21 CxTXQCON
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxTXQCONT: Accesses the top byte TXQCON[31:24]
- CxTXQCONU: Accesses the upper byte TXQCON[23:16]
- CxTXQCONH: Accesses the high byte TXQCON[15:8]
- CxTXQCONL: Accesses the low byte TXQCON[7:0]
- These bits can only be
modified in Configuration mode (OPMOD[2:0] =
100
.
Name: | CxTXQCON |
Offset: | 0x0150 |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PLSIZE[2:0] | FSIZE[4:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TXAT[1:0] | TXPRI[4:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FRESET | TXREQ | UINC | |||||||
Access | S/HC | R/W/HC | S/HC | ||||||
Reset | 1 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TXEN | TXATIE | TXQEIE | TXQNIE | ||||||
Access | R | R/W | R/W | R/W | |||||
Reset | 1 | 0 | 0 | 0 |
Bits 31:29 – PLSIZE[2:0] Payload Size(2)
Value | Description |
---|---|
111 | 64 data bytes |
110 | 48 data bytes |
101 | 32 data bytes |
100 | 24 data bytes |
011 | 20 data bytes |
010 | 16 data bytes |
001 | 12 data bytes |
000 | 8 data bytes |
Bits 28:24 – FSIZE[4:0] FIFO Size(2)
Value | Description |
---|---|
11111 | FIFO is 32 messages deep |
00010 | FIFO is 3 messages deep |
00001 | FIFO is 2 messages deep |
00000 | FIFO is 1 messages deep |
Bits 22:21 – TXAT[1:0] Retransmission Attempts
Value | Description |
---|---|
11 | Unlimited number of retransmission attempts |
10 | Unlimited number of retransmission attempts |
01 | Three retransmission attempts |
00 | Disable retransmission attempts |
Bits 20:16 – TXPRI[4:0] Message Transmit Priority
Value | Description |
---|---|
11111 | Highest message priority |
00000 | Lowest message priority |
Bit 10 – FRESET FIFO Reset
Value | Description |
---|---|
1 | FIFO will be reset when this bit is set, cleared by hardware when FIFO is reset; user needs to poll whether this bit is clear before taking any action |
0 | No effect |
Bit 9 – TXREQ Message Send Request
Value | Description |
---|---|
1 | Requests sending a message; the bit will automatically clear when all the messages queued in the TXQ are successfully sent |
0 | Clearing the bit to ‘0 ’ while set (‘1 ’)
will request a message abort. |
Bit 8 – UINC Increment Head/Tail
Bit 7 – TXEN TX Enable
Value | Description |
---|---|
1 | The
transmit message queue is always configured as a transmitter; this bit will
always read as ‘1 ’ |
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable
Value | Description |
---|---|
1 | Enables interrupt |
0 | Disables interrupt |
Bit 2 – TXQEIE Transmit Queue Empty Interrupt Enable
Value | Description |
---|---|
1 | Interrupt is enabled for TXQ empty |
0 | Interrupt is disabled for TXQ empty |
Bit 0 – TXQNIE Transmit QUeue Not Full Interrupt Enable
Value | Description |
---|---|
1 | Interrupt is enabled for TXQ not full |
0 | Interrupt is disabled for TXQ not full |