31 Instruction Set Summary

Note: This data sheet summarizes the features of the dsPIC33CK512MPT608 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip website (www.microchip.com).

The dsPIC33CK instruction set is almost identical to that of the dsPIC30F and dsPIC33F.

Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations.

Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped into five basic categories:

Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations

Table 1 lists the general symbols used in describing the instructions.

The dsPIC33 instruction set summary in Table 31-2 lists all the instructions, along with the status flags affected by each instruction.

Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands:

The first source operand, which is typically a register ‘Wb’ without any address modifier
The second source operand, which is typically a register ‘Ws’ with or without an address modifier
The destination of the result, which is typically a register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions have two operands:

The file register specified by the value ‘f’
The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’

Most bit-oriented instructions (including simple rotate/shift instructions) have two operands:

The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’)
The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)

The literal instructions that involve data movement can use some of the following operands:

A literal value to be loaded into a W register or file register (specified by ‘k’)
The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or logical operations use some of the following operands:

The first source operand, which is a register ‘Wb’ without any address modifier
The second source operand, which is a literal value
The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier

The MAC class of DSP instructions can use some of the following operands:

The accumulator (A or B) to be used (required operand)
The W registers to be used as the two operands
The X and Y address space prefetch operations
The X and Y address space prefetch destinations
The accumulator write-back destination

The other DSP instructions do not involve any multiplication and can include:

The accumulator to be used (required)
The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier
The amount of shift specified by a W register ‘Wn’ or a literal value

The control instructions can use some of the following operands:

A program memory address
The mode of the Table Read and Table Write instructions

Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the eight MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it executes as a NOP.

The double-word instructions execute in two instruction cycles.

Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruction, or a PSV or Table Read is performed. In these cases, the execution takes multiple instruction cycles, with the additional instruction cycle(s) executed as a NOP. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles.

Note: For more details on the instruction set, refer to the “16-Bit MCU and DSC Programmer’s Reference Manual” (www.microchip.com/DS70000157).

Table 31-1. Symbols Used in Opcode Descriptions
Field	Description
#text	Means literal defined by “`text`”
(text)	Means “content of `text`”
[text]	Means “the location addressed by `text`”
{ }	Optional field or operation
a ∈ {b, c, d}	a is selected from the set of values b, c, d
[n:m]	Register bit field
.b	Byte mode selection
.d	Double-Word mode selection
.S	Shadow register select
.w	Word mode selection (default)
Acc	One of two accumulators {A, B}
AWB	Accumulator Write-Back Destination Address register ∈ {W13, [W13]+ = 2}
bit4	4-bit bit selection field (used in word-addressed instructions) ∈ {0...15}
C, DC, N, OV, Z	MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr	Absolute address, label or expression (resolved by the linker)
f	File register address ∈ {0x0000...0x1FFF}
lit1	1-bit unsigned literal ∈ {0,1}
lit4	4-bit unsigned literal ∈ {0...15}
lit5	5-bit unsigned literal ∈ {0...31}
lit8	8-bit unsigned literal ∈ {0...255}
lit10	10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
lit14	14-bit unsigned literal ∈ {0...16384}
lit16	16-bit unsigned literal ∈ {0...65535}
lit23	23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘`0`’
None	Field does not require an entry, can be blank
OA, OB, SA, SB	DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC	Program Counter
Slit10	10-bit signed literal ∈ {-512...511}
Slit16	16-bit signed literal ∈ {-32768...32767}
Slit6	6-bit signed literal ∈ {-16...16}
Wb	Base W register ∈ {W0...W15}
Wd	Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo	Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn	Dividend, Divisor Working register pair (direct addressing)
Wm*Wm	Multiplicand and Multiplier Working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn	Multiplicand and Multiplier Working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn	One of 16 Working registers ∈ {W0...W15}
Wnd	One of 16 Destination Working registers ∈ {W0...W15}
Wns	One of 16 Source Working registers ∈ {W0...W15}
WREG	W0 (Working register used in file register instructions)
Ws	Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso	Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx	X Data Space Prefetch Address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none}
Wxd	X Data Space Prefetch Destination register for DSP instructions ∈ {W4...W7}
Wy	Y Data Space Prefetch Address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none}
Wyd	Y Data Space Prefetch Destination register for DSP instructions ∈ {W4...W7}
Note: In dsPIC33CK512MPT608 devices, read and Read-Modify-Write (RMW) operations on non-CPU Special Function Registers require an additional cycle when compared to dsPIC30F, dsPIC33F, PIC24F and PIC24H devices.

Table 31-2. Instruction Set Overview
Base Instr #	Assembly Mnemonic	Assembly Syntax		Description	# of Words	# of Cycles⁽¹⁾	Status Flags Affected
1	`ADD`	`ADD`	`Acc`	Add Accumulators	1	1	OA,OB,SA,SB
		`ADD`	`f`	f = f + WREG	1	1	C,DC,N,OV,Z
		`ADD`	`f,WREG`	WREG = f + WREG	1	1	C,DC,N,OV,Z
		`ADD`	`#lit10,Wn`	Wd = lit10 + Wd	1	1	C,DC,N,OV,Z
		`ADD`	`Wb,Ws,Wd`	Wd = Wb + Ws	1	1	C,DC,N,OV,Z
		`ADD`	`Wb,#lit5,Wd`	Wd = Wb + lit5	1	1	C,DC,N,OV,Z
		`ADD`	`Wso,#Slit4,Acc`	16-bit Signed Add to Accumulator	1	1	OA,OB,SA,SB
2	`ADDC`	`ADDC`	`f`	f = f + WREG + (C)	1	1	C,DC,N,OV,Z
		`ADDC`	`f,WREG`	WREG = f + WREG + (C)	1	1	C,DC,N,OV,Z
		`ADDC`	`#lit10,Wn`	Wd = lit10 + Wd + (C)	1	1	C,DC,N,OV,Z
		`ADDC`	`Wb,Ws,Wd`	Wd = Wb + Ws + (C)	1	1	C,DC,N,OV,Z
		`ADDC`	`Wb,#lit5,Wd`	Wd = Wb + lit5 + (C)	1	1	C,DC,N,OV,Z
3	`AND`	`AND`	`f`	f = f .AND. WREG	1	1	N,Z
		`AND`	`f,WREG`	WREG = f .AND. WREG	1	1	N,Z
		`AND`	`#lit10,Wn`	Wd = lit10 .AND. Wd	1	1	N,Z
		`AND`	`Wb,Ws,Wd`	Wd = Wb .AND. Ws	1	1	N,Z
		`AND`	`Wb,#lit5,Wd`	Wd = Wb .AND. lit5	1	1	N,Z
4	`ASR`	`ASR`	`f`	f = Arithmetic Right Shift f	1	1	C,N,OV,Z
		`ASR`	`f,WREG`	WREG = Arithmetic Right Shift f	1	1	C,N,OV,Z
		`ASR`	`Ws,Wd`	Wd = Arithmetic Right Shift Ws	1	1	C,N,OV,Z
		`ASR`	`Wb,Wns,Wnd`	Wnd = Arithmetic Right Shift Wb by Wns	1	1	N,Z
		`ASR`	`Wb,#lit5,Wnd`	Wnd = Arithmetic Right Shift Wb by lit5	1	1	N,Z
5	`BCLR`	`BCLR`	`f,#bit4`	Bit Clear f	1	1	None
5	`BCLR`	`BCLR`	`Ws,#bit4`	Bit Clear Ws	1	1	None
6	`BFEXT`	`BFEXT`	`bit4,wid5,Ws,Wb`	Bit Field Extract from Ws to Wb	2	2	None
6	`BFEXT`	`BFEXT`	`bit4,wid5,f,Wb`	Bit Field Extract from f to Wb	2	2	None
7	`BFINS`	`BFINS`	`bit4,wid5,Wb,Ws`	Bit Field Insert from Wb into Ws	2	2	None
		`BFINS`	`bit4,wid5,Wb,f`	Bit Field Insert from Wb into f	2	2	None
		`BFINS`	`bit4,wid5,lit8,Ws`	Bit Field Insert from #lit8 to Ws	2	2	None
8	`BOOTSWP`	`BOOTSWP`		Swap the Active and Inactive Program Flash Space	1	2	None
9	`BRA`	`BRA`	`C,Expr`	Branch if Carry	1	1 (4)/1	None
		`BRA`	`GE,Expr`	Branch if Greater Than or Equal	1	1 (4)/1	None
		`BRA`	`GEU,Expr`	Branch if unsigned Greater Than or Equal	1	1 (4)/1	None
		`BRA`	`GT,Expr`	Branch if Greater Than	1	1 (4)/1	None
		`BRA`	`GTU,Expr`	Branch if Unsigned Greater Than	1	1 (4)/1	None
		`BRA`	`LE,Expr`	Branch if Less Than or Equal	1	1 (4)/1	None
		`BRA`	`LEU,Expr`	Branch if Unsigned Less Than or Equal	1	1 (4)/1	None
		`BRA`	`LT,Expr`	Branch if Less Than	1	1 (4)/1	None
		`BRA`	`LTU,Expr`	Branch if Unsigned Less Than	1	1 (4)/1	None
		`BRA`	`N,Expr`	Branch if Negative	1	1 (4)/1	None
		`BRA`	`NC,Expr`	Branch if Not Carry	1	1 (4)/1	None
		`BRA`	`NN,Expr`	Branch if Not Negative	1	1 (4)/1	None
		`BRA`	`NOV,Expr`	Branch if Not Overflow	1	1 (4)/1	None
		`BRA`	`NZ,Expr`	Branch if Not Zero	1	1 (4)/1	None
		`BRA`	`OA,Expr`	Branch if Accumulator A Overflow	1	1 (4)/1	None
		`BRA`	`OB,Expr`	Branch if Accumulator B Overflow	1	1 (4)/1	None
		`BRA`	`OV,Expr`	Branch if Overflow	1	1 (4)/1	None
		`BRA`	`SA,Expr`	Branch if Accumulator A Saturated	1	1 (4)/1	None
		`BRA`	`SB,Expr`	Branch if Accumulator B Saturated	1	1 (4)/1	None
		`BRA`	`Expr`	Branch Unconditionally	1	4/2	None
		`BRA`	`Z,Expr`	Branch if Zero	1	1 (4)/1	None
		`BRA`	`Wn`	Computed Branch	1	4	None
10	`BREAK`	`BREAK`		Stop User Code Execution	1	1	None
11	`BSET`	`BSET`	`f,#bit4`	Bit Set f	1	1	None
11	`BSET`	`BSET`	`Ws,#bit4`	Bit Set Ws	1	1	None
12	`BSW`	`BSW.C`	`Ws,Wb`	Write C Bit to Ws[Wb]	1	1	None
12	`BSW`	`BSW.Z`	`Ws,Wb`	Write Z Bit to Ws[Wb]	1	1	None
13	`BTG`	`BTG`	`f,#bit4`	Bit Toggle f	1	1	None
13	`BTG`	`BTG`	`Ws,#bit4`	Bit Toggle Ws	1	1	None
14	`BTSC`	`BTSC`	`f,#bit4`	Bit Test f, Skip if Clear	1	1 (2 or 3)	None
14	`BTSC`	`BTSC`	`Ws,#bit4`	Bit Test Ws, Skip if Clear	1	1 (2 or 3)	None
15	`BTSS`	`BTSS`	`f,#bit4`	Bit Test f, Skip if Set	1	1 (2 or 3)	None
15	`BTSS`	`BTSS`	`Ws,#bit4`	Bit Test Ws, Skip if Set	1	1 (2 or 3)	None
16	`BTST`	`BTST`	`f,#bit4`	Bit Test f	1	1	Z
		`BTST.C`	`Ws,#bit4`	Bit Test Ws to C	1	1	C
		`BTST.Z`	`Ws,#bit4`	Bit Test Ws to Z	1	1	Z
		`BTST.C`	`Ws,Wb`	Bit Test Ws[Wb] to C	1	1	C
		`BTST.Z`	`Ws,Wb`	Bit Test Ws[Wb] to Z	1	1	Z
17	`BTSTS`	`BTSTS`	`f,#bit4`	Bit Test then Set f	1	1	Z
		`BTSTS.C`	`Ws,#bit4`	Bit Test Ws to C, then Set	1	1	C
		`BTSTS.Z`	`Ws,#bit4`	Bit Test Ws to Z, then Set	1	1	Z
18	`CALL`	`CALL`	`lit23`	Call Subroutine	2	4(2)	SFA
		`CALL`	`Wn`	Call Indirect Subroutine	1	4(2)	SFA
		`CALL.L`	`Wn`	Call Indirect Subroutine (long address)	1	4(2)	SFA
19	`CLR`	`CLR`	`f`	f = 0x0000	1	1	None
		`CLR`	`WREG`	WREG = 0x0000	1	1	None
		`CLR`	`Ws`	Ws = 0x0000	1	1	None
		`CLR`	`Acc,Wx,Wxd,Wy,Wyd,AWB`	Clear Accumulator	1	1	OA,OB,SA,SB
20	`CLRWDT`	`CLRWDT`		Clear Watchdog Timer	1	1	WDTO,Sleep
21	`COM`	`COM`	`f`	f = f	1	1	N,Z
		`COM`	`f,WREG`	WREG = f	1	1	N,Z
		`COM`	`Ws,Wd`	Wd = Ws	1	1	N,Z
22	`CP`	`CP`	`f`	Compare f with WREG	1	1	C,DC,N,OV,Z
		`CP`	`Wb,#lit8`	Compare Wb with lit8	1	1	C,DC,N,OV,Z
		`CP`	`Wb,Ws`	Compare Wb with Ws (Wb – Ws)	1	1	C,DC,N,OV,Z
23	`CP0`	`CP0`	`f`	Compare f with 0x0000	1	1	C,DC,N,OV,Z
23	`CP0`	`CP0`	`Ws`	Compare Ws with 0x0000	1	1	C,DC,N,OV,Z
24	`CPB`	`CPB`	`f`	Compare f with WREG, with Borrow	1	1	C,DC,N,OV,Z
		`CPB`	`Wb,#lit8`	Compare Wb with lit8, with Borrow	1	1	C,DC,N,OV,Z
		`CPB`	`Wb,Ws`	Compare Wb with Ws, with Borrow (Wb – Ws – C)	1	1	C,DC,N,OV,Z
25	`CPSEQ`	`CPSEQ`	`Wb,Wn`	Compare Wb with Wn, Skip if =	1	1 (2 or 3)	None
25	`CPBEQ`	`CPBEQ`	`Wb,Wn,Expr`	Compare Wb with Wn, Branch if =	1	1 (5)	None
26	`CPSGT`	`CPSGT`	`Wb,Wn`	Compare Wb with Wn, Skip if >	1	1 (2 or 3)	None
26	`CPBGT`	`CPBGT`	`Wb,Wn,Expr`	Compare Wb with Wn, Branch if >	1	1 (5)	None
27	`CPSLT`	`CPSLT`	`Wb,Wn`	Compare Wb with Wn, Skip if <	1	1 (2 or 3)	None
27	`CPSLT`	`CPBLT`	`Wb,Wn,Expr`	Compare Wb with Wn, Branch if <	1	1 (5)	None
28	`CPSNE`	`CPSNE`	`Wb,Wn`	Compare Wb with Wn, Skip if ≠	1	1 (2 or 3)	None
28	`CPSNE`	`CPBNE`	`Wb,Wn,Expr`	Compare Wb with Wn, Branch if ≠	1	1 (5)	None
29	`CTXTSWP`	`CTXTSWP`	`#1it3`	Switch CPU Register Context to Context Defined by lit3	1	2	None
30	`CTXTSWP`	`CTXTSWP`	`Wn`	Switch CPU Register Context to Context Defined by Wn	1	2	None
31	`DAW.B`	`DAW.B`	`Wn`	Wn = Decimal Adjust Wn	1	1	C
32	`DEC`	`DEC`	`f`	f = f – 1	1	1	C,DC,N,OV,Z
		`DEC`	`f,WREG`	WREG = f – 1	1	1	C,DC,N,OV,Z
		`DEC`	`Ws,Wd`	Wd = Ws – 1	1	1	C,DC,N,OV,Z
33	`DEC2`	`DEC2`	`f`	f = f – 2	1	1	C,DC,N,OV,Z
		`DEC2`	`f,WREG`	WREG = f – 2	1	1	C,DC,N,OV,Z
		`DEC2`	`Ws,Wd`	Wd = Ws – 2	1	1	C,DC,N,OV,Z
34	`DISI`	`DISI`	`#lit14`	Disable Interrupts for k Instruction Cycles	1	1	None
35	`DIVF`⁽²⁾	`DIVF`	`Wm,Wn`	Signed 16/16-Bit Fractional Divide	1	6	N,Z,C,OV
36	`DIV.S`⁽²⁾	`DIV.S`	`Wm,Wn`	Signed 16/16-Bit Integer Divide	1	6	N,Z,C,OV
36	`DIV.S`⁽²⁾	`DIV.SD`	`Wm,Wn`	Signed 32/16-Bit Integer Divide	1	6	N,Z,C,OV
37	`DIV.U`⁽²⁾	`DIV.U`	`Wm,Wn`	Unsigned 16/16-Bit Integer Divide	1	6	N,Z,C,OV
37	`DIV.U`⁽²⁾	`DIV.UD`	Wm,Wn	Unsigned 32/16-Bit Integer Divide	1	6	N,Z,C,OV
38	`DIVF2`⁽²⁾	`DIVF2`	`Wm,Wn`	Signed 16/16-Bit Fractional Divide (W1:W0 preserved)	1	6	N,Z,C,OV
39	`DIV2.S`⁽²⁾	`DIV2.S`	`Wm,Wn`	Signed 16/16-Bit Integer Divide (W1:W0 preserved)	1	6	N,Z,C,OV
39	`DIV2.S`⁽²⁾	`DIV2.SD`	`Wm,Wn`	Signed 32/16-Bit Integer Divide  (W1:W0 preserved)	1	6	N,Z,C,OV
40	`DIV2.U`⁽²⁾	`DIV2.U`	`Wm,Wn`	Unsigned 16/16-Bit Integer Divide  (W1:W0 preserved)	1	6	N,Z,C,OV
40	`DIV2.U`⁽²⁾	`DIV2.UD`	`Wm,Wn`	Unsigned 32/16-Bit Integer Divide  (W1:W0 preserved)	1	6	N,Z,C,OV
41	`DO`	`DO`	`#lit15,Exp`r	Do Code to PC + Expr, lit15 + 1 Times	2	2	None
41	`DO`	`DO`	`Wn,Expr`	Do code to PC + Expr, (Wn) + 1 Times	2	2	None
42	`ED`	`ED`	`Wm*Wm,Acc,Wx,Wy,Wxd`	Euclidean Distance (no accumulate)	1	1	OA,OB,OAB, SA,SB,SAB
43	`EDAC`	`EDAC`	`Wm*Wm,Acc,Wx,Wy,Wxd`	Euclidean Distance	1	1	OA,OB,OAB, SA,SB,SAB
44	`EXCH`	`EXCH`	`Wns,Wnd`	Swap Wns with Wnd	1	1	None
46	`FBCL`	`FBCL`	`Ws,Wnd`	Find Bit Change from Left (MSb) Side	1	1	C
47	`FF1L`	`FF1L`	`Ws,Wnd`	Find First One from Left (MSb) Side	1	1	C
48	`FF1R`	`FF1R`	`Ws,Wnd`	Find First One from Right (LSb) Side	1	1	C
49	`FLIM`	`FLIM`	`Wb, Ws`	Force Data (Upper and Lower) Range Limit without Limit Excess Result	1	1	N,Z,OV
49	`FLIM`	`FLIM.V`	`Wb, Ws, Wd`	Force Data (Upper and Lower) Range Limit with Limit Excess Result	1	1	N,Z,OV
50	`GOTO`	`GOTO`	`Expr`	Go to Address	2	4/2	None
		`GOTO`	`Wn`	Go to Indirect	1	4/2	None
		`GOTO.L`	`Wn`	Go to Indirect (long address)	1	4/2	None
51	`INC`	`INC`	`f`	f = f + 1	1	1	C,DC,N,OV,Z
		`INC`	`f,WREG`	WREG = f + 1	1	1	C,DC,N,OV,Z
		`INC`	`Ws,Wd`	Wd = Ws + 1	1	1	C,DC,N,OV,Z
52	`INC2`	`INC2`	`f`	f = f + 2	1	1	C,DC,N,OV,Z
		`INC2`	`f,WREG`	WREG = f + 2	1	1	C,DC,N,OV,Z
		`INC2`	`Ws,Wd`	Wd = Ws + 2	1	1	C,DC,N,OV,Z
53	`IOR`	`IOR`	`f`	f = f .IOR. WREG	1	1	N,Z
		`IOR`	`f,WREG`	WREG = f .IOR. WREG	1	1	N,Z
		`IOR`	`#lit10,Wn`	Wd = lit10 .IOR. Wd	1	1	N,Z
		`IOR`	`Wb,Ws,Wd`	Wd = Wb .IOR. Ws	1	1	N,Z
		`IOR`	`Wb,#lit5,Wd`	Wd = Wb .IOR. lit5	1	1	N,Z
54	`LAC`	`LAC`	`Wso,#Slit4,Acc`	Load Accumulator	1	1	OA,OB,OAB, SA,SB,SAB
54	`LAC`	`LAC.D`	`Wso, #Slit4, Acc`	Load Accumulator Double	1	2	OA,SA,OB,SB
56	`LNK`	`LNK`	`#lit14`	Link Frame Pointer	1	1	SFA
57	`LSR`	`LSR`	`f`	f = Logical Right Shift f	1	1	C,N,OV,Z
		`LSR`	`f,WREG`	WREG = Logical Right Shift f	1	1	C,N,OV,Z
		`LSR`	`Ws,Wd`	Wd = Logical Right Shift Ws	1	1	C,N,OV,Z
		`LSR`	`Wb,Wns,Wnd`	Wnd = Logical Right Shift Wb by Wns	1	1	N,Z
		`LSR`	`Wb,#lit5,Wnd`	Wnd = Logical Right Shift Wb by lit5	1	1	N,Z
58	`MAC`	`MAC`	`Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB`	Multiply and Accumulate	1	1	OA,OB,OAB, SA,SB,SAB
58	`MAC`	`MAC`	`Wm*Wm,Acc,Wx,Wxd,Wy,Wyd`	Square and Accumulate	1	1	OA,OB,OAB, SA,SB,SAB
59	`MAX`	`MAX`	`Acc`	Force Data Maximum Range Limit	1	1	N,OV,Z
59	`MAX`	`MAX.V`	`Acc, Wnd`	Force Data Maximum Range Limit with Result	1	1	N,OV,Z
60	`MIN`	`MIN`	`Acc`	If Accumulator A Less than B Load Accumulator with B or vice versa	1	1	N,OV,Z
		`MIN.V`	`Acc, Wd`	If Accumulator A Less than B Accumulator Force Minimum Data Range Limit with Limit Excess Result	1	1	N,OV,Z
		`MINZ`	`Acc`	Accumulator Force Minimum Data Range Limit	1	1	N,OV,Z
		`MINZ.V`	`Acc, Wd`	Accumulator Force Minimum Data Range Limit with Limit Excess Result	1	1	N,OV,Z
61	`MOV`	`MOV`	`f,Wn`	Move f to Wn	1	1	None
		`MOV`	`f`	Move f to f	1	1	None
		`MOV`	`f,WREG`	Move f to WREG	1	1	None
		`MOV`	`#lit16,Wn`	Move 16-Bit Literal to Wn	1	1	None
		`MOV.b`	`#lit8,Wn`	Move 8-Bit Literal to Wn	1	1	None
		`MOV`	`Wn,f`	Move Wn to f	1	1	None
		`MOV`	`Wso,Wdo`	Move Ws to Wd	1	1	None
		`MOV`	`WREG,f`	Move WREG to f	1	1	None
		`MOV.D Wns,Wd`		Move Double from W(ns):W(ns + 1) to Wd	1	2	None
		`MOV.D Ws,Wnd`		Move Double from Ws to W(nd + 1):W(nd)	1	2	None
62	`MOVPAG`	`MOVPAG`	`#lit10,DSRPAG`	Move 10-Bit Literal to DSRPAG	1	1	None
		`MOVPAG`	`#lit8,TBLPAG`	Move 8-Bit Literal to TBLPAG	1	1	None
		`MOVPAG`	`Ws, DSRPAG`	Move Ws[9:0] to DSRPAG	1	1	None
		`MOVPAG`	`Ws, TBLPAG`	Move Ws[7:0] to TBLPAG	1	1	None
64	`MOVSAC`	`MOVSAC`	`Acc,Wx,Wxd,Wy,Wyd,AWB`	Prefetch and Store Accumulator	1	1	None
65	`MPY`	`MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd`		Multiply Wm by Wn to Accumulator	1	1	OA,OB,OAB, SA,SB,SAB
65	`MPY`	`MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd`		Square Wm to Accumulator	1	1	OA,OB,OAB, SA,SB,SAB
66	`MPY.N`	`MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd`		-(Multiply Wm by Wn) to Accumulator	1	1	None
67	`MSC`	`MSC`	`Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB`	Multiply and Subtract from Accumulator	1	1	OA,OB,OAB, SA,SB,SAB
68	`MUL`	`MUL.SS`	`Wb,Ws,Wnd`	{Wnd + 1, Wnd} = Signed(Wb) * Signed(Ws)	1	1	None
		`MUL.SS`	`Wb,Ws,Acc`	Accumulator = Signed(Wb) * Signed(Ws)	1	1	None
		`MUL.SU`	`Wb,Ws,Wnd`	{Wnd + 1, Wnd} = Signed(Wb) * Unsigned(Ws)	1	1	None
		`MUL.SU`	`Wb,Ws,Acc`	Accumulator = Signed(Wb) * Unsigned(Ws)	1	1	None
		`MUL.SU`	`Wb,#lit5,Acc`	Accumulator = Signed(Wb) * Unsigned(lit5)	1	1	None
		`MUL.US`	`Wb,Ws,Wnd`	{Wnd + 1, Wnd} = Unsigned(Wb) * Signed(Ws)	1	1	None
		`MUL.US`	`Wb,Ws,Acc`	Accumulator = Unsigned(Wb) * Signed(Ws)	1	1	None
		`MUL.UU`	`Wb,Ws,Wnd`	{Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(Ws)	1	1	None
		`MUL.UU`	`Wb,#lit5,Acc`	Accumulator = Unsigned(Wb) * Unsigned(lit5)	1	1	None
		`MUL.UU`	`Wb,Ws,Acc`	Accumulator = Unsigned(Wb) * Unsigned(Ws)	1	1	None
		`MULW.SS`	`Wb,Ws,Wnd`	Wnd = Signed(Wb) * Signed(Ws)	1	1	None
		`MULW.SU`	`Wb,Ws,Wnd`	Wnd = Signed(Wb) * Unsigned(Ws)	1	1	None
		`MULW.US`	`Wb,Ws,Wnd`	Wnd = Unsigned(Wb) * Signed(Ws)	1	1	None
		`MULW.UU`	`Wb,Ws,Wnd`	Wnd = Unsigned(Wb) * Unsigned(Ws)	1	1	None
		`MUL.SU`	`Wb,#lit5,Wnd`	{Wnd + 1, Wnd} = Signed(Wb) * Unsigned(lit5)	1	1	None
		`MUL.SU`	`Wb,#lit5,Wnd`	Wnd = Signed(Wb) * Unsigned(lit5)	1	1	None
		`MUL.UU`	`Wb,#lit5,Wnd`	{Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(lit5)	1	1	None
		`MUL.UU`	`Wb,#lit5,Wnd`	Wnd = Unsigned(Wb) * Unsigned(lit5)	1	1	None
		`MUL`	`f`	W3:W2 = f * WREG	1	1	None
69	`NEG`	`NEG`	`Acc`	Negate Accumulator	1	1	OA,OB,OAB, SA,SB,SAB
		`NEG`	`f`	f = f + 1	1	1	C,DC,N,OV,Z
		`NEG`	`f,WREG`	WREG = f + 1	1	1	C,DC,N,OV,Z
		`NEG`	`Ws,Wd`	Wd = Ws + 1	1	1	C,DC,N,OV,Z
70	`NOP`	`NOP`		No Operation	1	1	None
70	`NOP`	`NOPR`		No Operation	1	1	None
71	`NORM`	`NORM`	`Acc, Wd`	Normalize Accumulator	1	1	N,OV,Z
72	`POP`	`POP`	`f`	Pop f from Top-of-Stack (TOS)	1	1	None
		`POP`	`Wdo`	Pop from Top-of-Stack (TOS) to Wdo	1	1	None
		`POP.D`	`Wnd`	Pop from Top-of-Stack (TOS) to  W(nd):W(nd + 1)	1	2	None
		`POP.S`		Pop Shadow Registers	1	1	All
73	`PUSH`	`PUSH`	`f`	Push f to Top-of-Stack (TOS)	1	1	None
		`PUSH`	`Wso`	Push Wso to Top-of-Stack (TOS)	1	1	None
		`PUSH.D`	`Wns`	Push W(ns):W(ns + 1) to Top-of-Stack (TOS)	1	2	None
		`PUSH.S`		Push Shadow Registers	1	1	None
74	`PWRSAV`	`PWRSAV #lit1`		Go into Sleep or Idle mode	1	1	WDTO,Sleep
75	`RCALL`	`RCALL`	`Expr`	Relative Call	1	4/2⁽²⁾	SFA
75	`RCALL`	`RCALL`	`Wn`	Computed Call	1	4/2⁽²⁾	SFA
76	`REPEAT`	`REPEAT`	`#lit15`	Repeat Next Instruction lit15 + 1 Times	1	1	None
76	`REPEAT`	`REPEAT`	`Wn`	Repeat Next Instruction (Wn) + 1 Times	1	1	None
77	`RESET`	`RESET`		Software Device Reset	1	1	None
78	`RETFIE`	`RETFIE`		Return from Interrupt	1	6 (5)/3⁽²⁾	SFA
79	`RETLW`	`RETLW`	`#lit10,Wn`	Return with Literal in Wn	1	6 (5)/3⁽²⁾	SFA
80	`RETURN`	`RETURN`		Return from Subroutine	1	6 (5)/3⁽²⁾	SFA
81	`RLC`	`RLC`	`f`	f = Rotate Left through Carry f	1	1	C,N,Z
		`RLC`	`f,WREG`	WREG = Rotate Left through Carry f	1	1	C,N,Z
		`RLC`	`Ws,Wd`	Wd = Rotate Left through Carry Ws	1	1	C,N,Z
82	`RLNC`	`RLNC`	`f`	f = Rotate Left (No Carry) f	1	1	N,Z
		`RLNC`	`f,WREG`	WREG = Rotate Left (No Carry) f	1	1	N,Z
		`RLNC`	`Ws,Wd`	Wd = Rotate Left (No Carry) Ws	1	1	N,Z
83	`RRC`	`RRC`	`f`	f = Rotate Right through Carry f	1	1	C,N,Z
		`RRC`	`f,WREG`	WREG = Rotate Right through Carry f	1	1	C,N,Z
		`RRC`	`Ws,Wd`	Wd = Rotate Right through Carry Ws	1	1	C,N,Z
84	`RRNC`	`RRNC`	`f`	f = Rotate Right (No Carry) f	1	1	N,Z
		`RRNC`	`f,WREG`	WREG = Rotate Right (No Carry) f	1	1	N,Z
		`RRNC`	`Ws,Wd`	Wd = Rotate Right (No Carry) Ws	1	1	N,Z
85	`SAC`	`SAC`	`Acc,#Slit4,Wdo`	Store Accumulator	1	1	None
		`SAC.R`	`Acc,#Slit4,Wdo`	Store Rounded Accumulator	1	1	None
		`SAC.D`	`#Slit4, Wdo`	Store Accumulator Double	1	1	None
86	`SE`	`SE`	`Ws,Wnd`	Wnd = Sign-Extended Ws	1	1	C,N,Z
87	`SETM`	`SETM`	`f`	f = 0xFFFF	1	1	None
		`SETM`	`WREG`	WREG = 0xFFFF	1	1	None
		`SETM`	`Ws`	Ws = 0xFFFF	1	1	None
88	`SFTAC`	`SFTAC`	`Acc,Wn`	Arithmetic Shift Accumulator by (Wn)	1	1	OA,OB,OAB, SA,SB,SAB
88	`SFTAC`	`SFTAC`	`Acc,#Slit6`	Arithmetic Shift Accumulator by Slit6	1	1	OA,OB,OAB, SA,SB,SAB
89	`SL`	`SL`	`f`	f = Left Shift f	1	1	C,N,OV,Z
		`SL`	`f,WREG`	WREG = Left Shift f	1	1	C,N,OV,Z
		`SL`	`Ws,Wd`	Wd = Left Shift Ws	1	1	C,N,OV,Z
		`SL`	`Wb,Wns,Wnd`	Wnd = Left Shift Wb by Wns	1	1	N,Z
		`SL`	`Wb,#lit5,Wnd`	Wnd = Left Shift Wb by lit5	1	1	N,Z
91	`SUB`	`SUB`	`Acc`	Subtract Accumulators	1	1	OA,OB,OAB, SA,SB,SAB
		`SUB`	`f`	f = f – WREG	1	1	C,DC,N,OV,Z
		`SUB`	`f,WREG`	WREG = f – WREG	1	1	C,DC,N,OV,Z
		`SUB`	`#lit10,Wn`	Wn = Wn – lit10	1	1	C,DC,N,OV,Z
		`SUB`	`Wb,Ws,Wd`	Wd = Wb – Ws	1	1	C,DC,N,OV,Z
		`SUB`	`Wb,#lit5,Wd`	Wd = Wb – lit5	1	1	C,DC,N,OV,Z
92	SUBB	`SUBB`	`f`	f = f – WREG – (C)	1	1	C,DC,N,OV,Z
		`SUBB`	`f,WREG`	WREG = f – WREG – (C)	1	1	C,DC,N,OV,Z
		`SUBB`	`#lit10,Wn`	Wn = Wn – lit10 – (C)	1	1	C,DC,N,OV,Z
		`SUBB`	`Wb,Ws,Wd`	Wd = Wb – Ws – (C)	1	1	C,DC,N,OV,Z
		`SUBB`	`Wb,#lit5,Wd`	Wd = Wb – lit5 – (C)	1	1	C,DC,N,OV,Z
93	`SUBR`	`SUBR`	`f`	f = WREG – f	1	1	C,DC,N,OV,Z
		`SUBR`	`f,WREG`	WREG = WREG – f	1	1	C,DC,N,OV,Z
		`SUBR`	`Wb,Ws,Wd`	Wd = Ws – Wb	1	1	C,DC,N,OV,Z
		`SUBR`	`Wb,#lit5,Wd`	Wd = lit5 – Wb	1	1	C,DC,N,OV,Z
94	`SUBBR`	`SUBBR`	`f`	f = WREG – f – (C)	1	1	C,DC,N,OV,Z
		`SUBBR`	`f,WREG`	WREG = WREG – f – (C)	1	1	C,DC,N,OV,Z
		`SUBBR`	`Wb,Ws,Wd`	Wd = Ws – Wb – (C)	1	1	C,DC,N,OV,Z
		`SUBBR`	`Wb,#lit5,Wd`	Wd = lit5 – Wb – (C)	1	1	C,DC,N,OV,Z
95	`SWAP`	`SWAP.b`	`Wn`	Wn = Nibble Swap Wn	1	1	None
95	`SWAP`	`SWAP`	`Wn`	Wn = Byte Swap Wn	1	1	None
96	`TBLRDH`	`TBLRDH`	`Ws,Wd`	Read Prog[23:16] to Wd[7:0]	1	5/3	None
97	`TBLRDL`	`TBLRDL`	`Ws,Wd`	Read Prog[15:0] to Wd	1	5/3	None
98	`TBLWTH`	`TBLWTH`	`Ws,Wd`	Write Ws[7:0] to Prog[23:16]	1	2	None
99	`TBLWTL`	`TBLWTL`	`Ws,Wd`	Write Ws to Prog[15:0]	1	2	None
101	`ULNK`	`ULNK`		Unlink Frame Pointer	1	1	SFA
104	`XOR`	`XOR`	`f`	f = f .XOR. WREG	1	1	N,Z
		`XOR`	`f,WREG`	WREG = f .XOR. WREG	1	1	N,Z
		`XOR`	`#lit10,Wn`	Wd = lit10 .XOR. Wd	1	1	N,Z
		`XOR`	`Wb,Ws,Wd`	Wd = Wb .XOR. Ws	1	1	N,Z
		`XOR`	`Wb,#lit5,Wd`	Wd = Wb .XOR. lit5	1	1	N,Z
105	`ZE`	`ZE`	`Ws,Wnd`	Wnd = Zero-Extend Ws	1	1	C,Z,N
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. For dsPIC33CK512MPT608 devices, the divide instructions must be preceded with a “`REPEAT #5`” instruction, such that they are executed six consecutive times.