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Digital Signal Controllers with Secure Subsystem
Description
Operating Conditions
Core: dsPIC33CK CPU
Advanced Flash Features
Security Features
Safety Features
Clock Management
Power Management
High-Resolution PWM with Fine Edge Placement
Timers/Output Compare/Input Capture
Advanced Analog Features
Communication Interfaces
Direct Memory Access (DMA)
Additional Peripheral Features
Debugger Development Support
Functional Safety Readiness – ISO 26262/IEC 61508/IEC 60730
Qualification Support
dsPIC33CK512MPT608 Product Families
Pin Diagram
To Our Valued Customers
Referenced Sources
Terminology Cross Reference
1 Device Overview
2 Guidelines for Getting Started with Digital Signal Controllers
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 Master Clear (MCLR) Pin
2.4 ICSP Pins
2.5 External Oscillator Pins
2.6 External Oscillator Layout Guidance
2.7 Oscillator Value Conditions on Device Start-up
2.8 Unused I/Os
2.9 Bulk Capacitors
2.10 Targeted Applications
3 CPU
3.1 Registers
3.2 Instruction Set
3.3 Data Space Addressing
3.4 Addressing Modes
3.5 CPU Control/Status Registers
3.6 Arithmetic Logic Unit (ALU)
3.7 DSP Engine
4 Memory Organization
4.1 Program Address Space
4.2 Data Address Space
4.3 BIST Overview
4.4 Memory Resources
5 Flash Program Memory
5.1 Table Instructions and Flash Programming
5.2 RTSP Operation
5.3 Error Correcting Code (ECC)
5.4 ECC Fault Injection
5.5 Flash OTP by ICSP™ Write Inhibit
5.6 Dual Partition Flash Configuration
5.7 NVM/ECC Control Registers
6 Secure Subsystem
6.1 Overview
6.2 Features
6.3 SPI Clock Configuration
6.4 Applications
7 Resets
7.1 Reset Resources
8 Interrupt Controller
8.1 Interrupt Vector Table
8.2 Alternate Interrupt Vector Table
8.3 Reset Sequence
8.4 Interrupt Resources
8.5 Interrupt Control and Status Registers
8.6 Status/Control Registers
8.7 Status/Control Registers
9 I/O Ports
9.1 Parallel I/O (PIO) Ports
9.2 Configuring Analog and Digital Port Pins
9.3 Input Change Notification (ICN)
9.4 Peripheral Pin Select (PPS)
9.5 Considerations for Peripheral Pin Selection
9.6 Input Mapping
9.7 Virtual Connections
9.8 Output Mapping
9.9 Mapping Limitations
9.10 I/O Helpful Tips
9.11 I/O Ports Resources
9.12 Peripheral Pin Select Control Registers
10 Oscillator with High-Frequency PLL
10.1 Primary PLL
10.2 Auxiliary PLL
10.3 CPU Clocking
10.4 Primary Oscillator (POSC)
10.5 Internal Fast RC (FRC) Oscillator
10.6 Low-Power RC Oscillator
10.7 Backup Internal Fast RC (BFRC) Oscillator
10.8 Reference Clock Output
10.9 Oscillator Configuration
10.10 OSCCON Unlock Sequence
10.11 Oscillator Control Registers
11 Direct Memory Access (DMA) Controller
11.1 Summary of DMA Operations
11.2 Typical Setup
12 Controller Area Network Flexible Data-Rate (CAN FD) Modules
12.1 Features
12.2 CAN Control/Status Registers
13 High-Resolution PWM with Fine Edge Placement
13.1 Features
13.2 Architecture Overview
13.3 Lock and Write Restrictions
13.4 PWM4H/L Output on Peripheral Pin Select
13.5 PWM Control/Status Registers
13.6 Control Registers
14 High-Speed, 12-Bit Analog-to-Digital Converter
14.1 ADC Features Overview
14.2 Temperature Sensor
14.3 ADC Control Registers
14.4 Analog-to-Digital Converter Resources
15 High-Speed Analog Comparator with Slope Compensation DAC
15.1 Overview
15.2 Features Overview
15.3 DAC Control Registers
15.4 DAC Control Registers
16 Quadrature Encoder Interface (QEI)
16.1 QEI Control/Status Registers
17 Universal Asynchronous Receiver Transmitter (UART)
17.1 Architectural Overview
17.2 Character Frame
17.3 Data Buffers
17.4 Protocol Extensions
17.5 UART Control/Status Registers
18 Serial Peripheral Interface (SPI)
18.1 SPI Control/Status Registers
19 Inter-Integrated Circuit (I2C)
19.1 Communicating as a Host in a Single Host Environment
19.2 Setting Baud Rate When Operating as a Bus Main
19.3 Client Address Masking
19.4 SMBus Support
19.5 I2C Control/Status Registers
20 Single-Edge Nibble Transmission (SENT)
20.1 Transmit Mode
20.2 Receive Mode
20.3 SENT Control/Status Registers
21 Timer1
21.1 Timer1 Control Register
22 Capture/Compare/PWM/Timer Modules (SCCP)
22.1 Time Base Generator
22.2 General Purpose Timer
22.3 Output Compare Mode
22.4 Input Capture Mode
22.5 Auxiliary Output
22.6 SCCP Control/Status Registers
23 Configurable Logic Cell (CLC)
23.1 CLC Control Registers
24 Peripheral Trigger Generator (PTG)
24.1 Features
24.2 PTG Registers
24.3 PTG Step Commands
25 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
25.1 CRC Control Registers
26 Current Bias Generator (CBG)
26.1 Current Bias Generator Control Registers
27 Operational Amplifier
27.1 Operational Amplifier Control Registers
28 Deadman Timer (DMT)
28.1 Deadman Timer Control/Status Registers
29 Power-Saving Features
29.1 Clock Frequency and Clock Switching
29.2 Instruction-Based Power-Saving Modes
29.3 Doze Mode
29.4 Peripheral Module Disable
29.5 Power-Saving Resources
29.6 Power-Saving Control Registers
30 Special Features
30.1 Configuration Bits
30.2 Configuration Registers
30.3 Device Calibration and Identification
30.4 User OTP Memory
30.5 On-Chip Voltage Regulators
30.6 Brown-out Reset (BOR)
30.7 Dual Watchdog Timer (WDT)
30.8 JTAG Interface
30.9 In-Circuit Debugger
30.10 Code Protection and CodeGuard™ Security
31 Instruction Set Summary
32 Development Support
33 Electrical Characteristics
33.1 DC Characteristics
33.2 AC Characteristics and Timing Parameters
34 Packaging Information
34.1 Package Marking Information
34.2 Package Details
35 Revision History
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