10 Oscillator with High-Frequency PLL
Note: This data sheet summarizes the
features of the dsPIC33CK512MPT608 family of devices. It is not intended
to be a comprehensive reference source. To complement the information in this data
sheet, refer to “Oscillator Module with High-Speed PLL” (www.microchip.com/DS70005255) in the “dsPIC33/PIC24 Family Reference
Manual”.
The dsPIC33CK512MPT608 family oscillator with high-frequency PLL includes these characteristics:
- On-Chip Phase-Locked Loop (PLL) to Boost Internal Operating Frequency on Select Internal and External Oscillator Sources
- Auxiliary PLL (APLL) Clock Generator to Boost Operating Frequency for Peripherals
- Doze mode for System Power Savings
- Scalable Reference Clock Output (REFCLKO)
- On-the-Fly Clock Switching between Various Clock Sources
- Fail-Safe Clock Monitoring (FSCM) that Detects Clock Failure and Permits Safe Application Recovery or Shutdown
A block diagram of the dsPIC33CK512MPT608 oscillator system is shown in Figure 1.