18 Serial Peripheral Interface (SPI)

Note: This data sheet summarizes the features of the dsPIC33CK512MPT608 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Serial Peripheral Interface (SPI) with Audio Codec Support” (www.microchip.com/DS70005136) in the “dsPIC33/PIC24 Family Reference Manual”.

The Serial Peripheral Interface (SPI) module is a synchronous serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with the Motorola® SPI and SIOP interfaces. All devices in the dsPIC33CK512MPT608 family include three SPI modules.

Note: This family of devices has three SPIs. However, one of them is used for communication with the Secure Subsystem. Only two are available for general purpose.

The module supports operation in two Buffer modes. In Standard mode, data are shifted through a single serial buffer. In Enhanced Buffer mode, data are shifted through a FIFO buffer. The FIFO level depends on the configured mode.

Note: FIFO depth for this device is four (in 8-Bit Data mode).

Variable length data can be transmitted and received, from 2 to 32 bits.

Note: Do not perform Read-Modify-Write operations (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode.

The module also supports Audio modes. Four different Audio modes are available.

  • I2S mode
  • Left Justified mode
  • Right Justified mode
  • PCM/DSP mode

In each of these modes, the serial clock is free-running and audio data are always transferred.

The SPI serial interface consists of four pins:

  • SDIx: Serial Data Input
  • SDOx: Serial Data Output
  • SCKx: Shift Clock Input or Output

The SPI module can be configured to operate using two, three or four pins.

The SPI module has the ability to generate three interrupts, reflecting the events that occur during the data communication. The following types of interrupts can be generated:

  1. Receive interrupts are signaled by SPIxRXIF. This event occurs when:
    • RX watermark interrupt
    • SPIROV = 1
    • SPIRBF = 1
    • SPIRBE = 1

    provided the respective mask bits are enabled in SPIxIMSKL/H.

  2. Transmit interrupts are signalled by SPIxTXIF. This event occurs when:
    • TX watermark interrupt
    • SPITUR = 1
    • SPITBF = 1
    • SPITBE = 1

    provided the respective mask bits are enabled in SPIxIMSKL/H.

  3. General interrupts are signalled by SPIxGIF. This event occurs when:
    • FRMERR = 1
    • SPIBUSY = 1
    • SRMT = 1

    provided the respective mask bits are enabled in SPIxIMSKL/H.

Block diagrams of the module in Standard and Enhanced modes are shown in Figure 18-1 and Figure 18-2.

Note: In this section, the SPI modules are referred to together as SPIx, or separately as SPI1, SPI2 or SPI3. Special Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for any of the three SPI modules.

To set up the SPIx module for the Standard Host mode of operation:

  1. If using interrupts:
    1. Clear the interrupt flag bits in the respective IFSx register.
    2. Set the interrupt enable bits in the respective IECx register.
    3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
  2. Write the desired settings to the SPIxCON1L and SPIxCON1H registers with the MSTEN bit (SPIxCON1L[5]) = 1.
  3. Clear the SPIROV bit (SPIxSTATL[6]).
  4. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
  5. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.

To set up the SPIx module for the Standard Client mode of operation:

  1. Clear the SPIxBUF registers.
  2. If using interrupts:
    1. Clear the SPIxBUFL and SPIxBUFH registers.
    2. Set the interrupt enable bits in the respective IECx register.
    3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
  3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with the MSTEN bit (SPIxCON1L[5]) = 0.
  4. Clear the SMP bit.
  5. If the CKE bit (SPIxCON1L[8]) is set, then the SSEN bit (SPIxCON1L[7]) must be set to enable the SSx pin.
  6. Clear the SPIROV bit (SPIxSTATL[6]).
  7. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
Figure 18-1. SPIx Module Block Diagram (Standard Mode)

To set up the SPIx module for the Enhanced Buffer Host mode of operation:

  1. If using interrupts:
    1. Clear the interrupt flag bits in the respective IFSx register.
    2. Set the interrupt enable bits in the respective IECx register.
    3. Write the SPIxIP bits in the respective IPCx register.
  2. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with MSTEN (SPIxCON1L[5]) = 1.
  3. Clear the SPIROV bit (SPIxSTATL[6]).
  4. Select Enhanced Buffer mode by setting the ENHBUF bit (SPIxCON1L[0]).
  5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
  6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.

To set up the SPIx module for the Enhanced Buffer Client mode of operation:

  1. Clear the SPIxBUFL and SPIxBUFH registers.
  2. If using interrupts:
    1. Clear the interrupt flag bits in the respective IFSx register.
    2. Set the interrupt enable bits in the respective IECx register.
    3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
  3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with the MSTEN bit (SPIxCON1L[5]) = 0.
  4. Clear the SMP bit.
  5. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin.
  6. Clear the SPIROV bit (SPIxSTATL[6]).
  7. Select Enhanced Buffer mode by setting the ENHBUF bit (SPIxCON1L[0]).
  8. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
Figure 18-2. SPIx Module Block Diagram (Enhanced Mode)

To set up the SPIx module for Audio mode:

  1. Clear the SPIxBUFL and SPIxBUFH registers.
  2. If using interrupts:
    1. Clear the interrupt flag bits in the respective IFSx register.
    2. Set the interrupt enable bits in the 
respective IECx register.
    3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
  3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with AUDEN (SPIxCON1H[15]) = 1.
  4. Clear the SPIROV bit (SPIxSTATL[6]).
  5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
  6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.
Figure 18-3. SPIx Main Connection (Standard Mode)
Figure 18-4. SPIx Main Connection (Enhanced Buffer Modes)
Equation 18-1. Relationship Between Device and SPIx Clock Speed