Core: dsPIC33CK CPU

• 256-512 Kbytes of Program Flash with ECC and 64 Kbytes of Data RAM
• Fast Six-Cycle Divide
• LiveUpdate
• Code-Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus Hardware Divide
• 32-Bit Multiply Support
• Five Sets of Interrupt Context Selected Registers for Fast Interrupt Response
• Zero Overhead Looping
• RAM Memory Built-In Self-Test (MBIST)