3 CPU
The dsPIC33CK512MPT608 family CPU has a (data) modified Harvard architecture with an enhanced instruction set, including significant support for Digital Signal Processing (DSP). The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain throughput and provides
predictable execution. Most instructions execute in a single-cycle effective execution
rate, with the exception of instructions that change the program flow, the double-word move
(MOV.D
) instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported using the DO
and
REPEAT
instructions, both of which are interruptible at any point.