3.10.7.2.1.6 T1MR – Timer1 Mode Register

Name:	T1MR
Offset:	0x071
Reset:	0x00

This register must only be modified while the timer is disabled (T1CR.T1ENA = 0). Modifying the bits during operation leads to unpredictable operation.


Bit	7	6	5	4	3	2	1	0
	T1DC[1:0]		T1PS[3:0]				T1CS[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – T1DC[1:0] Timer1 Duty Cycle

The T1DC1 and T1DC0 bits select the duty cycle mode of the duty cycle generator as shown in the following table.

Table 3-90. Timer1 Duty Cycle Bit Description
T1DC1	T1DC0	Function of the Duty Cycle Generator	Additional Divider Effect
`0`	`0`	Bypassed (DCG0)	1
`0`	`1`	Duty cycle 1/1 (DCG1)	2
`1`	`0`	Duty cycle 1/2 (DCG2)	3
`1`	`1`	Duty cycle 1/3 (DCG3)	4

Bits 5:2 – T1PS[3:0] Timer1 Prescaler Select

The T1PS[3:0] bits select the prescaler value of Timer1 as shown in the following formulas:

p r e s c a l e r V a l u e = 2^{T 2 P S [3 : 0]} ......(47)

{C L 1 P}_{F r e q u e n c y} = \frac{{C L 1}_{F r e q u e n c y}}{p r e s c a l e r V a l u e} = \frac{{C L 1}_{F r e q u e n c y}}{2^{T 2 P S [3 : 0]}} ......(48)

T1PS[3:0] ∈ {0..15}

Bits 1:0 – T1CS[1:0] Timer1 Clock Select

The T1CS[1:0] bits select the input clock (CL1) of Timer1 as shown in the following table.

Table 3-91. Timer1 Input Clock Select Bit Description
T1CS[1:0]		Input Clock (CL1) of Timer
`0`	`0`	CLK_SRC
`0`	`1`	CLK_VDIV
`1`	`0`	CLK_T
`1`	`1`	CLK_XTO4