3.10.7.6.1.1 T5CCR – Timer5 Configuration and Control Register
| Name: | T5CCR |
| Offset: | 0x08C |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T5CTC | T5CS[2:0] | ||||||||
| Access | R | R | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
0’.Bit 6 – Reserved Bit
0’.Bit 5 – Reserved Bit
0’.Bit 4 – Reserved Bit
0’.Bit 3 – T5CTC Clear Counter on Compare Match
Bits 2:0 – T5CS[2:0] Clock Select
| T5CS[2:0] | Description | ||
|---|---|---|---|
0 | 0 | 0 | No clock source (Timer/counter stopped) |
0 | 0 | 1 | CLKI/O/1 (No prescaling) |
0 | 1 | 0 | CLKI/O/8 (From prescaler) |
0 | 1 | 1 | CLKI/O/32 (From prescaler) |
1 | 0 | 0 | CLKI/O/64 (From prescaler) |
1 | 0 | 1 | CLKI/O/128 (From prescaler) |
1 | 1 | 0 | CLKI/O/256 (From prescaler) |
1 | 1 | 1 | CLKI/O/1024 (From prescaler) |