3.4.3.2.1.6 DMCRB – Demodulator Control Register

This register must only be modified if the block receiving the settings is disabled (RDPR.PRPTB = 1). Modifying the settings during operation may lead to unstable operation.

Name:	DMCRB
Offset:	0x0A5
Reset:	0x00


Bit	7	6	5	4	3	2	1	0
	DMARB	SY1TB	SASKB	DMPGB[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – DMARB Demodulator Automatic Restart on Path B

This bit enables a hardware-controlled automatic restart of the demodulator and the subsequent receiving path B.


Bit 7	Description
`0`	The reception and demodulation is continued regardless of error events.
`1`	Reception and demodulation are restarted if any activated condition for the EOTB interrupt is true. The EOTB condition status flags (EOTS[3:0]) and the SOTB condition status flags (SOTSB) are cleared at every restart. The restart is automatically performed by toggling the RDPR.PRPTB bit. The PRPTB bit is not writable while the automatic mode is active.

Bit 6 – SY1TB Symbol Check with 1T only on Path B

Activates a more rigorous check during symbol timing check.


Bit 6	Description
`0`	The symbol timing check accepts HIGH and LOW times with the selected symbol period (1T) and the double symbol period (2T). Random Manchester data can be used as preamble in this mode.
`1`	The symbol timing check allows HIGH and LOW times with the selected symbol rate only. This corresponds to an alternating preamble of `1` and `0` symbols. It is a more rigorous criterion, and, therefore, leads to shorter average on-times. The 1T check is performed for the number of bits specified in the SYCSB register. Afterward, 1T and 2T are acceptable (corresponding to random Manchester).

Bit 5 – SASKB Select ASK Input for Path B


Bit 5	Description
`0`	FSK input is selected for receiving path B
`1`	ASK input is selected for receiving path B

Bits 4:0 – DMPGB[4:0] Demodulator PLL Loop Gain for Path B

The correct settings for this register are provided by the configuration tool after selecting the target deviation and data rate for path B. They can also be calculated by using the following procedure:

Calculation of the target PLL loop gain for the maximum symbol rate

$S Y M_G A I N_B = 5 \times \frac{S y m b o l R a t e P a t h B}{C L K_B B} ......(25)$

Equation parameters:
- SymbolRatePathB: Maximum expected symbol rate in Hz on the useful signal for path B
- CLK_BB: Baseband clock frequency in Hz. See equation (13) in the section Bandwidth Scaling

Calculation of the target PLL loop gain for the maximum deviation

$D E V_G A I N_B = 10 \times \frac{D e v i a t a i o n R a t e P a t h B}{C L K_B B} .......(26)$

Equation parameters:
- DeviationPathB: Maximum expected frequency deviation in Hz of the useful signal for path B
- CLK_BB: Baseband clock frequency in Hz. See equation (13) in the section Bandwidth Scaling
Select the required PLL loop gain which is the larger one of the two gains.
$R E Q_P L L_G A I N = \max (S Y M_G A I N_B, D E V_G A I N_B) ......(27)$
Select the DMPGB value according to the required PLL loop gain.
- The PLL_GAIN_B must be selected from the following table to be greater than or equal to the REQ_PLL_GAIN.
- If REQ_PLL_GAIN ≥ 1, set DMPGB = 16. The corresponding DMPGB value is the correct setting for this register.

Table 3-19. PLL Gain on Path B versus DMPGB Setting
PLL_GAIN_B	DMPGB(Dec)
0.06	0
0.08	1
0.09	2
0.11	3
0.13	4
0.16	5
0.19	6
0.22	7
0.25	8
0.31	9
0.38	10
0.44	11
0.50	12
0.63	13
0.75	14
0.88	15
≥ 1.00	16