3.4.3.2.1.3 DMDRA – Demodulator Data Rate on Path A
The target symbol rate for the receiving path A is configured in this register. This
register must only be modified if the block receiving the settings is disabled
(RDPR.PRPTA = 1
). Modifying the settings during operation may lead
to unstable operation.
Name: | DMDRA |
Offset: | 0x0A8 |
Reset: | 0x00 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DMDNA[3:0] | DMAA[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 7:4 – DMDNA[3:0] Demodulator Down-Sampling on Path A
DMDNA | ATSCAL_A |
---|---|
0 | 1 |
1 | 1 |
2 | 2 |
3 | 2 |
4 | 4 |
5 | 4 |
6 | 8 |
7 | 8 |
8 | 16 |
DMDNA = floor [Id (20) + Id (CLK_BBSymbolRatePathA × 128)]......(18)
If the result is -1, set DMDNA = 0
- Equation parameters:
- SymbolRatePathA: Maximum expected symbol rate in Hz on the useful signal for path A
- CLK_BB: Baseband clock frequency in Hz. See equation (13) in the section Bandwidth Scaling
- ld(): Logarithm to the base 2
Bits 3:0 – DMAA[3:0] Demodulator Moving Average Data Rate Factor on Path A
DMAA | MAVFL_A | SR_F_A |
---|---|---|
0 | 12 | 10 |
1 | 11 | 11 |
2 | 10 | 12 |
3 | 9 | 13 |
4 | 9 | 14 |
5 | 8 | 15 |
6 | 8 | 16 |
7 | 7 | 17 |
8 | 7 | 18 |
9 | 6 | 19 |
10 | 6 | 20 |
11 | 6 | 21 |
12 | 5 | 22 |
13 | 5 | 24 |
14 | 4 | 26 |
15 | 4 | 28 |
SR_F_A = round (SymbolRatePathA × 2DMDNA × 128CLK_BB).......(19)
- Equation parameters:
- SymbolRatePathA: Maximum expected symbol rate in Hz on the useful signal for path A
- CLK_BB: Baseband clock frequency in Hz. See equation (13) in the section Bandwidth Scaling
- SR_F_A: Must be in the range of 10 to 28, if possible 10 to 19