3.4.3.6.1.1 RSSC – RSSI Configuration Register

Name: RSSC
Offset: 0x151
Reset: 0x00

Bit 76543210 
 RSPKFRSHRXRSWLHRSUP[3:0] 
Access RR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 –  Reserved Bit

This bit is reserved and returns ‘0’ when read.

Bit 6 – RSPKF RSSI Peak Values to SFIFO

RSIFCDescription
0RSSI average values are forwarded to the SFIFO.
1RSSI peak values are forwarded to the SFIFO.

Bit 5 – RSHRX RSSI High-Band Reception

High- or Low-Band reception is selected for antenna-damping RSSI compensation. See the RSCOM.RSDC bit description for details.

Bit 4 – RSWLH RSSI within Low and High Limits

Selects the valid received signal range in relation to the limit registers.
RSWLHDescription
0A valid signal is expected to be outside the low and high limits set by the RSSL and RSSH registers. This mode can be used to reject signals within a certain RSSI range.
1A valid signal is expected to be within the limits set by the RSSIL and RSSIH registers. This mode can be used to only accept signals within a certain RSSI range.
Figure 3-17. RSWLH Working Principle

Bits 3:0 – RSUP[3:0] RSSI Update Period

Selects the update period for RSSI averaging and peak calculation. The register setting for a desired update period can be calculated:
RSUP⁢ =  round⁢ (log⁡2(update_period⁢ × fCLK_BB))......(42)

update_period: Required update period in s

fCLK_BB: Baseband clock frequency in Hz. See equation (13) in section Bandwidth Scaling