47.12 Fractional Digital Phase Locked Loop (FDPLL96M) Electrical Specifications
| AC CHARACTERISTICS | Standard
Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +125°C for Extended Temp |
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|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
| FDPLL96M (Fractional Digital Phase Locked Loop) | |||||||
| FDPLL_5 | FDPLL_Jitter (1, 2) | FDPLL96M Period Jitter Pk-to-Pk | 1.4 | — | 4.2 | % | VDD = VDDIO = 5.0V, fIN = 32.768 kHz from XOSC32K, fOUT = 48 MHz |
| 1 | — | 13.5 | % | VDD = VDDIO = 5.0V, fIN = 32.768 kHz from XOSC32K, fOUT = 96 MHz |
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| FDPLL_7 | 1.4 | — | 4.8 | % | VDD = VDDIO = 5.0V, fIN = 2 MHz from XOSC, fOUT = 48 MHz |
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| 1 | — | 10.6 | % | VDD = VDDIO = 5.0V, fIN = 2 MHz from XOSC, fOUT = 96 MHz |
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Note:
- REFCLK for FDPLL96M is XOSC or XOSC32K.
- DPLL jitter is sensitive to digital on-chip activity, which is application dependent.