AN4594

1.8.3.4 Probe Insertion

Probe insertion is a post-layout debug process that enables internal nets in the FPGA design to be routed to unused or used I/Os. Nets are selected and assigned to probes using the Probe Insertion tab in SmartDebug. The rerouted design is reprogrammed automatically by Libero into the FPGA, where an external logic analyzer or oscilloscope can be used to view the activity of the probed signal. The following figure shows the Probe Insertion tab in the Debug FPGA Array window.

Figure 1-23. Debug FPGA Array—Probe Insertion

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