1.8.3 Debug FPGA Array

The Debug FPGA Array provides an interface to probe the user logic implemented in the FPGA's Logic Elements (LEs) using active and live probes, and read-write access to the fabric flip-flops, and read-write access to the memories implemented using DPSRAMs/URAMs. Probe insertion allows the assignment of the internal signals to the assigned or unassigned pins. These signals can be monitored using the oscilloscope in real-time. The Debug FPGA Array supports the following four features:

• Live Probes
• Active Probes
• Memory Blocks
• Probe Insertion