35.10.4 System Clock

Table 35-13. System Clock Timing Characteristics
Symbol	Description	Min.	Typ. ✝	Max.	Unit	Conditions
f_{CLK_CPU} f_{CLK_PER}	System clock frequency, industrial temperature range⁽¹⁾	0	—	4	MHz	-40°C ≤ T_A ≤ +85°C 1.62V ≤ V_DD < 1.8V
		0	—	5	MHz	-40°C ≤ T_A ≤ +85°C 1.8V ≤ V_DD < 2.7V
		0	—	10	MHz	-40°C ≤ T_A ≤ +85°C 2.7V ≤ V_DD < 4.5V
		0	—	20	MHz	-40°C ≤ T_A ≤ +85°C V_DD ≥ 4.5V
	System clock frequency, extended temperature range⁽¹⁾	0	—	3.4	MHz	-40°C ≤ T_A ≤ +125°C 1.62V ≤ V_DD < 1.8V
		0	—	4	MHz	-40°C ≤ T_A ≤ +125°C 1.8V ≤ V_DD < 2.7V
		0	—	8	MHz	-40°C ≤ T_A ≤ +125°C 2.7V ≤ V_DD < 4.5V
		0	—	16	MHz	-40°C ≤ T_A ≤ +125°C V_DD ≥ 4.5V
f_CY	Instruction clock frequency	—	f_{CLK_CPU}	—	MHz
T_CY	Instruction cycle period⁽²⁾	50	1/f_CY	—	ns
✝ Data in the “Typ.” column is measured at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. Note: The system clock frequency (CLK_CPU) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section. Instruction Cycle Period (T_CY) is equal to the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in incorrect code execution and/or higher than expected current consumption. All devices are tested to operate at ‘Min.’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘Max.’ cycle time limit is ‘DC’ (no clock) for all devices.

The maximum CPU clock frequency depends on V_DD. As shown in the following figure, the maximum frequency vs. V_DD is linear between 1.62V < V_DD < 1.8V, 1.8V < V_DD < 2.7V, and 2.7V < V_DD < 4.5V.

Figure 35-3. Maximum Frequency vs. V_DD for [-40, 85]°C, Industrial Temperature

Figure 35-4. Maximum Frequency vs. V_DD for [-40, 125]°C, Extended Temperature