4.17.18.40 PMC PLL Interrupt Mask Register

This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.

Name:	PMC_PLL_IMR
Offset:	0x00E8
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
		UNLOCK6	UNLOCK5	UNLOCK4	UNLOCK3	UNLOCK2	UNLOCK1	UNLOCK0
Access		W	W	W	W	W	W	W
Reset		0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
								LOCK8
Access								W
Reset								0


Bit	7	6	5	4	3	2	1	0
	LOCK7	LOCK6	LOCK5	LOCK4	LOCK3	LOCK2	LOCK1	LOCK0
Access	W	W	W	W	W	W	W	W
Reset	0	0	0	0	0	0	0	0

Bits 16, 17, 18, 19, 20, 21, 22 – UNLOCKx PLL of Index x Unlock Interrupt Mask

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – LOCKx PLL of Index x Lock Interrupt Mask

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.