4.17.18.7 PMC PLL Analog Control Register
This register must be loaded with the recommended values described in the Electrical Characteristics section.
All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.
| Name: | PMC_PLL_ACR |
| Offset: | 0x0018 |
| Reset: | 0x00000030 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LOOP_FILTER[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LOCK_THR[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UTMIBG | UTMIVR | CONTROL[11:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CONTROL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | |
Bits 29:24 – LOOP_FILTER[5:0] Loop Filter Selection
Bits 18:16 – LOCK_THR[2:0] PLL Lock Threshold Value Selection
Bit 13 – UTMIBG USBPLL Bandgap Control
| Value | Description |
|---|---|
| 0 | The USBPLL bandgap is switched off. |
| 1 | The USBPLL bandgap is switched on. |
Bit 12 – UTMIVR USBPLL Voltage Regulator Control
| Value | Description |
|---|---|
| 0 | The USBPLL voltage regulator is switched off. |
| 1 | The USBPLL voltage regulator is switched on. |