4.17.18.5 PMC PLL Control Register 1

All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.

Name:	PMC_PLL_CTRL1
Offset:	0x0010
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	MUL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			FRACR[21:16]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	FRACR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FRACR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – MUL[7:0] Multiplier Factor Value

Configures the internal clock frequency. See Divider and Phase Lock Loop Programming.

Bits 21:0 – FRACR[21:0] Fractional Loop Divider Setting

The FRACR field sent to the USBPLL is FRACR[13:0] and "00000000", which means that bits [21:14] are not used for the USBPLL.

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