19.7.4 Interrupt Flag Status and Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PLLxLOCKF | PLLxLOCKR | ||||||||
| Access | RW | RW | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLFAIL | DFLLRCS | DFLLUNF | DFLLOVF | DFLLLOCK | DFLLRDY | ||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKFAIL | XOSCFAIL | XOSCRDY | |||||||
| Access | RW | RW | RW | ||||||
| Reset | 0 | 0 | 0 |
Bit 25 – PLLxLOCKF PLL x Lock Fall
Bit 24 – PLLxLOCKR PLL x Lock Rise
Bit 13 – DFLLFAIL DFLL Startup Failure
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Startup Failure bit in the Status register (STATUS.DFLLFAIL) and will generate an interrupt request if INTENSET.DFLLFAIL is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Startup Failure interrupt flag.
Bit 12 – DFLLRCS DFLL Reference Clock Stopped
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS. DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag.
Bit 11 – DFLLUNF DFLL Tuner Underflow
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Tuner Underflow bit in the Status register (STATUS.DFLLUNF) and will generate an interrupt request if INTENSET.DFLLUNF is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Tuner Underflow interrupt flag.
Bit 10 – DFLLOVF DFLL Tuner Overflow
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Tuner Overflow bit in the Status register (STATUS.DFLLOVF) and will generate an interrupt request if INTENSET.DFLLOVF is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Tuner Overflow interrupt flag.
Bit 9 – DFLLLOCK DFLL Lock
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Lock bit in the Status register (STATUS.DFLLLOCK) and will generate an interrupt request if INTENSET.DFLLLOCK is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Lock interrupt flag.
Bit 8 – DFLLRDY DFLL Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the DFLL Ready interrupt flag.
Bit 2 – CLKFAIL XOSC Clock Failure
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC Clock Failure bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the XOSC Clock Failure interrupt flag.
Bit 1 – XOSCFAIL XOSC Startup Failure
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC Startup Failure bit in the Status register (STATUS.XOSCFAIL) and will generate an interrupt request if INTENSET.XOSCFAIL is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the XOSC Startup Failure interrupt flag.
Bit 0 – XOSCRDY XOSC Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'.
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit clears the XOSC Ready interrupt flag.