19.7.18 PLL Control

Table 19-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PLL1CTRL
Offset:	0x54
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
			BWSEL[2:0]			REFSEL[2:0]
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND					WRTLOCK	ENABLE
Access	RW					RW	RW
Reset	0					0	0

Bits 13:11 – BWSEL[2:0] Bandwidth selection

Value	Name	Description
0x0	BWSEL0	TBD
0x1	BWSEL1	TBD
0x2	BWSEL2	TBD
0x3	BWSEL3	TBD
0x4	BWSEL4	TBD
0x5	BWSEL5	TBD
0x6	BWSEL6	TBD
0x7	BWSEL7	TBD

Bits 10:8 – REFSEL[2:0] Reference selection

Value	Name	Description
0x0	GCLK	Dedicated GCLK clock reference
0x1	XOSC	XOSC clock reference
0x2	DFLL48M	DFLL48M clock reference

Bit 7 – ONDEMAND On Demand Control

Bit 2 – WRTLOCK Write Lock

Bit 1 – ENABLE PLL Enable

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