19.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	EVCTRL	31:24
		23:16
		15:8
		7:0								CFDEO
0x04	INTENCLR	31:24							PLLxLOCKF	PLLxLOCKR
		23:16
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		7:0						CLKFAIL	XOSCFAIL	XOSCRDY
0x08	INTENSET	31:24							PLLxLOCKF	PLLxLOCKR
		23:16
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		7:0						CLKFAIL	XOSCFAIL	XOSCRDY
0x0C	INTFLAG	31:24							PLLxLOCKF	PLLxLOCKR
		23:16
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		7:0						CLKFAIL	XOSCFAIL	XOSCRDY
0x10	STATUS	31:24								PLLxLOCK
		23:16
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		7:0					XOSCCKSW	CLKFAIL	XOSCFAIL	XOSCRDY
0x14	XOSCCTRLA	31:24	WRTLOCK						USBHSDIV[1:0]
		23:16					CFDPRESC[3:0]
		15:8					STARTUP[3:0]
		7:0	ONDEMAND		SWBEN	CFDEN	XTALEN	AGC	ENABLE
0x18	XOSCCTRLB	31:24	WRTLOCK
		23:16
		15:8
		7:0	USRCFG[7:0]
0x1C ... 0x2B	Reserved
0x2C	DFLLCTRLA	31:24
		23:16
		15:8
		7:0	ONDEMAND				LOWFREQ	WRTLOCK	ENABLE
0x30	DFLLCTRLB	31:24
		23:16
		15:8
		7:0	WAITLOCK		QLDIS	CCDIS	USBCRM	LLAW	STABLE	LOOPEN
0x34	DFLLTUNE	31:24
		23:16
		15:8
		7:0		TUNE[6:0]
0x38	DFLLDIFF	31:24
		23:16
		15:8	DIFF[15:8]
		7:0	DIFF[7:0]
0x3C	DFLLMUL	31:24
		23:16		STEP[6:0]
		15:8	MUL[15:8]
		7:0	MUL[7:0]
0x40	PLL0CTRL	31:24
		23:16
		15:8			BWSEL[2:0]			REFSEL[2:0]
		7:0	ONDEMAND					WRTLOCK	ENABLE
0x44	PLL0FBDIV	31:24
		23:16
		15:8							FBDIV[9:8]
		7:0	FBDIV[7:0]
0x48	PLL0REFDIV	31:24
		23:16
		15:8
		7:0			REFDIV[5:0]
0x4C	PLL0POSTDIVA	31:24
		23:16
		15:8
		7:0	OUTEN		POSTDIV[5:0]
0x50	PLL0POSTDIVB	31:24
		23:16
		15:8
		7:0	OUTEN		POSTDIV[5:0]
0x54	PLL1CTRL	31:24
		23:16
		15:8			BWSEL[2:0]			REFSEL[2:0]
		7:0	ONDEMAND					WRTLOCK	ENABLE
0x58	PLL1FBDIV	31:24
		23:16
		15:8							FBDIV[9:8]
		7:0	FBDIV[7:0]
0x5C	PLL1REFDIV	31:24
		23:16
		15:8
		7:0			REFDIV[5:0]
0x60	PLL1POSTDIVA	31:24
		23:16
		15:8
		7:0	OUTEN		POSTDIV[5:0]
0x64	PLL1POSTDIVB	31:24
		23:16
		15:8
		7:0	OUTEN		POSTDIV[5:0]
0x68 ... 0x6B	Reserved
0x6C	FRACDIV0	31:24		INTDIV[14:8]
		23:16	INTDIV[7:0]
		15:8	REMDIV[8:1]
		7:0	REMDIV[0]
0x70 ... 0x73	Reserved
0x74	FRACDIV1	31:24		INTDIV[14:8]
		23:16	INTDIV[7:0]
		15:8	REMDIV[8:1]
		7:0	REMDIV[0]
0x78	SYNCBUSY	31:24
		23:16
		15:8
		7:0	FRACDIV1	FRACDIV0	DFLLMUL	DFLLDIFF	DFLLTUNE	DFLLCTRLB	DFLLENABLE
0x7C ... 0x7F	Reserved
0x80	XOSCCAL	31:24
		23:16
		15:8	CAL[15:8]
		7:0	CAL[7:0]
0x84 ... 0x87	Reserved
0x88	RC48MCAL0	31:24	CAL[31:24]
		23:16	CAL[23:16]
		15:8	CAL[15:8]
		7:0	CAL[7:0]