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19.7.16 PLL output clock divider A
Important: The PLL0 frequency
cannot be changed on the fly while it's the active enabled clock to the system.
Table 19-21. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: PLL0POSTDIVA Offset: 0x4C Reset: 0x20202020 Property: RW
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 OUTEN POSTDIV[5:0] Access RW RW RW RW RW RW RW Reset 0 1 0 0 0 0 0
Bit 7 – OUTEN PLL output 0 enable
Bits 5:0 – POSTDIV[5:0] PLL output 0 clock division factor
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