19.7.6 External Multipurpose Crystal Oscillator Control A

Table 19-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
	WRTLOCK						USBHSDIV[1:0]
Access	RW						RW	RW
Reset	0						0	0


Bit	23	22	21	20	19	18	17	16
					CFDPRESC[3:0]
Access					RW	RW	RW	RW
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
					STARTUP[3:0]
Access					RW	RW	RW	RW
Reset					1	1	0	1


Bit	7	6	5	4	3	2	1	0
	ONDEMAND		SWBEN	CFDEN	XTALEN	AGC	ENABLE
Access	RW		RW	RW	RW	RW	RW
Reset	0		0	0	0	0	0

Bit 31 – WRTLOCK Write Lock for CTRLA register

Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.

Value	Description
0	The XOSCCTRLA register can be modified by a system write.
1	The XOSCCTRLA (except XOSCCTRLA.SWBEN) register is write protected.

Bits 25:24 – USBHSDIV[1:0] USBHS Referrence Clock Division

Value	Name	Description
0	DIS	USBHS PLL reference XOSC clock is disabled
1	DIV1	USBHS PLL reference XOSC clock is divided by 1
2	DIV2	USBHS PLL reference XOSC clock is divided by 2
3	DIV4	USBHS PLL reference XOSC clock is divided by 4

Bits 19:16 – CFDPRESC[3:0] Clock Failure Detector Prescaler

These bits select the DFLL48oscillator post scaler for the clock fail detector. The CFD safe clock frequency is the DFLL48 frequency divided by 2^CFDPRESC. These bits are XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE=1

Value	Name	Description
0	DIV1	48 MHz
1	DIV2	24 MHz
2	DIV4	12 MHz
3	DIV8	6 MHz
4	DIV16	3 MHz
5	DIV32	1.5 MHz
6	DIV64	0.75 MHz
7	DIV128	0.375 MHz
8	DIV256	187.5 KHz
9	DIV512	93.75 KHz
10	DIV1024	46.875 KHz
11	DIV2048	23.437 KHz
12	DIV4096	11.718 KHz
13	DIV8192	5.85 KHz
14	DIV16384	2.92 KHz
15	DIV32768	1.46 KHz

Bits 11:8 – STARTUP[3:0] Start-Up Time

These bits select start-up time for the oscillator XOSC according to the table below before a clock fail is acknowledged. The OSCULP32K oscillator is used to clock the start-up counter. These bits are XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.


STARTUP[3:0]	Number of OSCULP32KClock Cycles	Approximate Equivalent Time
0x0	1	31µs
0x1	2	61μs
0x2	4	122μs
0x3	8	244μs
0x4	16	488μs
0x5	32	977μs
0x6	64	1953μs
0x7	128	3906μs
0x8	256	7813μs
0x9	512	15625μs
0xA	1024	31250μs
0xB	2048	62500μs
0xC	4096	125000μs
0xD (Default)	8192	250000μs
0xE	16384	500000μs
0xF	32768	1000000μs

Note:

It is critical when using AGC to allow ample startup time to avoid spurious CFD events.
When using AGC BW = 0x0, the minimum startup time is 6.25 ms.

Value	Name	Description
0	CYCLE1	31 us
1	CYCLE2	61 us
2	CYCLE4	122 us
3	CYCLE8	244 us
4	CYCLE16	488 us
5	CYCLE32	977 us
6	CYCLE64	1953 us
7	CYCLE128	3906 us
8	CYCLE256	7813 us
9	CYCLE512	15625 us
10	CYCLE1024	31250 us
11	CYCLE2048	62500 us
12	CYCLE4096	125000 us
13	CYCLE8192	250000 us
14	CYCLE16384	500000 us
15	CYCLE32768	1000000 us

Bit 7 – ONDEMAND On Demand Control

The ONDEMAND operation mode allows the XOSC to be enabled or disabled depending on peripheral clock requests.

Note: The XOSC is not running if no peripheral is requesting the clock source.

If ONDEMAND is set, the XOSC will only be running when requested by a peripheral and enabled (XOSCTRLA.ENABLE = 1). If there is no peripheral requesting the XOSC’s clock source, the XOSC will be in a disabled state. If ONDEMAND is disabled, the XOSC will always be running when enabled (XOSCTRLA.ENABLE = 1). In Standby Sleep mode, the ONDEMAND operation is still active. This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.

Value	Description
0	The XOSC is always on.
1	The XOSC is running when a peripheral is requesting the XOSC to be used as a clock source.

Bit 5 – SWBEN Xosc Clock Switch Back Enable

This bit controls the XOSC output clock switch back to the external clock or crystal oscillator in case of clock recovery.

Note: The SWBEN bit is also cleared when the Clock Failure Detector is disabled (CFDEN = 0).

Value	Description
0	The clock switch back is disabled.
1	The clock switch back is enabled. This bit is reset once the XOSC output clock is switched back to the external clock or crystal oscillator.

Bit 4 – CFDEN Clock Failure Detector Enable

This bit controls the XOSC clock failure detector and is enable protected

Note: After setting CFDEN to enable clock failure detection, STATUS.CLKFAIL will always be set. This first detection must be ignored. Subsequent setting of this bit will indicate actual clock failure events.

Value	Description
0	Clock Failure Detector is disabled.
1	Clock Failure Detector is enabled.

Bit 3 – XTALEN Crystal Oscillator Enable

This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC.

Note:

If XOSCCTRLA.XTALEN = 0 then XOSCCTRLA.AGC = 1 is not permitted.
This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.
If XOSCCTRLA.XTALEN = 0 then XOSCCTRLB.GMAN (User Manual Gain control) bits are ignored.

Value	Description
0	External clock oscillator connected on XIN. XOUT can be used as general-purpose I/O.
1	Crystal connected to XIN and XOUT.

Bit 2 – AGC Auto Gain Control Loop Enable

Note:

If XOSCCTRLA.XTALEN = 0 then XOSCCTRLA.AGC = 1 is not permitted.
This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.
If AGC is enabled, XOSCCTRLB.GMAN (User Manual Gain control) bits are ignored.
When the XOSCCTRLA.AGC = 1, the Primary Oscillator will automatically do a linear search to find the lowest power/gain setting to guarantee stable oscillation with the user’s crystal.

Value	Description
0	The oscillator auto gain control loop is disabled.
1	The oscillator auto gain control loop is enabled.

Bit 1 – ENABLE Oscillator Enable

Value	Description
0	The oscillator XOSC is disabled.
1	The oscillator XOSC is enabled.

Name:	XOSCCTRLA
Offset:	0x14
Reset:	0x00000D00
Property:	RW