19.7.13 PLL Control

Table 19-17. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: PLL0CTRL
Offset: 0x40
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   BWSEL[2:0]REFSEL[2:0] 
Access RWRWRWRWRWRW 
Reset 000000 
Bit 76543210 
 ONDEMAND    WRTLOCKENABLE  
Access RWRWRW 
Reset 000 

Bits 13:11 – BWSEL[2:0] Bandwidth selection

These bits select the PLL closed loop filter bandwidth, depending on the frequency after the reference divider FPFD as shown in the table below. Selecting the correct filter bandwidth is important to operate the PLL'VCO in its best range.

Table 19-18. PLL0 BWSEL Filter
FPFDBWSEL[2:0]
Reserved0b000
4MHz ≤ FPFD < 10MHz0b001
10MHz ≤ FPFD < 20MHz0b010
20MHz ≤ FPFD < 30MHz0b011
30MHz ≤ FPFD < 60MHz0b100
Reserved0b101 – 0b111
Note:
  1. FPFD is the frequency of the reference clock divided by the PLL0 reference divider PLLREFDIV.REFDIV. These bits are PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE =1.
  2. At elevated temperatures, the effective range of the Bandwidth setting will skew higher. Depending on the input frequency and operating temperature, it may be optimal to change the BWSEL setting to the next higher value.
ValueNameDescription
0x0BWSEL0TBD
0x1BWSEL1TBD
0x2BWSEL2TBD
0x3BWSEL3TBD
0x4BWSEL4TBD
0x5BWSEL5TBD
0x6BWSEL6TBD
0x7BWSEL7TBD

Bits 10:8 – REFSEL[2:0] Reference selection

These bits select the PLL0 clock reference, as shown in the table below.

REFSEL[2:0]SelectedsourceDescription
0x0 (2,3)GCLKDedicated GCLK_PLL0_REF clock reference
0x1XOSCXOSC clock reference
0x2DFLL48MDFLL48M clock reference
0x3- 0x7n/aReserved
Note:
  1. These bits are PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE =1.
  2. IMPORTANT: If GCLK source is PLL0 then you should not use GCLK_PLL0_REF as input clock source to PLL0. It would create a circular reference, an unstable clock and unexpected behavior.
  3. The recommended clock sources for PLL0 are XOSC and the DFLL48M. Using the GLCK as a source is not recommended.
ValueNameDescription
0x0GCLKDedicated GCLK clock reference
0x1XOSCXOSC clock reference
0x2DFLL48MDFLL48M clock reference

Bit 7 – ONDEMAND On Demand Control

The ONDEMAND operation mode allows the PLL to be enabled or disabled depending on peripheral clock requests.

Note: If ONDEMAND is set, the PLL will only be running when requested by a peripheral and enabled (PLLCTRL. ENABLE = 1). If there is no peripheral requesting the PLL’s clock source, the PLL will be in a disabled state. If ONDEMAND is disabled, the PLL will always be running when enabled (PLLCTRL.ENABLE = 1). In Standby Sleep mode, the ONDEMAND operation is still active.

This bit is PLLCTRL0.ENABLE protected and cannot be updated if PLLCTRL0.ENABLE = 1.

ValueDescription
0The PLL0 is always on.
1The PLL0 is running when a peripheral is requesting the PLL to be used as a clock source. The PLL is not running if no peripheral is requesting the PLL clock source.

Bit 2 – WRTLOCK Write Lock

Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.
ValueDescription
0The PLLCTRL, PLLFBDIV, PLLREFDIV and PLLPOSTDIVA/B registers can be modified by a system write.
1The PLLCTRL, PLLFBDIV, PLLREFDIV and PLLPOSTDIVA/B registers are write protected, except for bits PLLPOSTDIVA.OUTENn.

Bit 1 – ENABLE PLL Enable

ValueDescription
0The PLL0 oscillator is disabled.
1The PLL0 oscillator is enabled.