31.5.14 PFM Write Protect Region n REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PWP |
| Offset: | 0x50 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PWPBASE[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PWPBASE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWPEN | PWPLOCK | PWPMIR | PWPSIZE[11:8] | ||||||
| Access | R/W | R/S | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWPSIZE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 27:16 – PWPBASE[11:0] The Region Base Address is PWPBASE * 4096 When PWPEN=1, the region from PWPBASE*4096 to PWPBASE*4096+PWPSIZE+1 is write/erase protected. Note: This field can only be modified when PWPLOCK=0, BUSY=0 and KEY=<CFGKEY Value>.
The Region Base Address is PWPBASE * 4096.
When PWPEN=1, the region from PWPBASE to PWPBASE+PWPSIZE+1 is write/erase protected.
Note: This is a byte address force to
align to page boundaries.
Note: This field can only be modified
when PWPLOCK=0, STATUS.BUSY=0 and KEY.KEY=<CFGKEY Value>.
Bit 15 – PWPEN Note: This field can only be modified when PWPLOCK=0, BUSY=0 and KEY=<CFGKEY Value>.
Note: This field can only be modified
when PWPLOCK=0, STATUS.BUSY=0 and KEY.KEY=<CFGKEY Value>.
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | PWP is Enabled for the defined region |
| 0 | DISABLE | PWP is Not Enabled for the defined region |
Bit 14 – PWPLOCK Note: PWPLOCK can be set the same time as other bits are written.
Note: PWPLOCK can be set the same
time as PWPBASE and PWPSIZE are written. Once set, PWPLOCK can only be cleared
by a reset (Writing zero has no effect.).
Note: This field can only be modified
when PWPLOCK=0, STATUS.BUSY=0 and KEY.KEY=<CFGKEY Value>.
| Value | Name | Description |
|---|---|---|
| 1 | LOCKED | This register is Locked and cannot be modified |
| 0 | UNLOCKED | This register is Not Locked and can be modified |
Bit 13 – PWPMIR Mirrors Lower PFM settings to Upper or Upper PFM settings to Lower. Used to maintain WP consistency between Upper and Lower PFM when using PFSWAP. Note: This field can only be modified when PWPLOCK=0, BUSY=0 and KEY=<CFGKEY Value>. Note: Mirroring is only valid for a dual panel flash system.
Mirrors Lower PFM settings to Upper or Upper PFM settings to Lower. This feature can be used to maintain Write Protect (WP) consistency between Upper and Lower PFM when using PFSWAP.
Note: When Mirrored, the PWPBASE
address bit that distinguishes between Upper and Lower PFM is treated as a
“Don’t Care”, meaning it can be 0 or 1.
Note: This field can only be modified
when PWPLOCK=0, STATUS.BUSY=0 and KEY.KEY=<CFGKEY Value>.
| Value | Name | Description |
|---|---|---|
| 1 | MIRROR | PWP settings are Mirrored |
| 0 | UNMIRROR | PWP settings are NOT Mirrored |
Bits 11:0 – PWPSIZE[11:0] Region Size is (PWPSIZE+1) * 4096. 0x000 = 4KB 0x001 = 8KB ... 0xFFF = 16MB Note: This field can only be modified when PWPLOCK=0, BUSY=0 and KEY=<CFGKEY Value>.
Pages Region Size is (PWPSIZE+1) *4KB.
0x000= 4KB
0x001= 8KB
...
0x3F= 256KB
Note: This field can only be modified
when PWPLOCK=0, STATUS.BUSY=0 and KEY.KEY=<CFGKEY Value>.