Bits 31:0 – ADDR[31:0] This is a system byte address that the FCW aligns (by dropping lower ordered bits) to the minimum resolution of the NVMOP.
Bulk/Chip/PFM Erase
Address is ignored
Page Erase
Address identifies the page to erase
Row Write
Address identifies the row to write
Condition: {PFM_DATA_MSB==63}
Double Write (64-bits)
Address identifies the Double Word to write. (ADDR[2:0] always read as 0.)
Condition: {PFM_DATA_MSB==127}
Single Write (32-bits)
Address identifies the Word to write. (ADDR[1:0] always read as 0.)
Quad Write (128-bits)
Address identifies the QWord to write. (ADDR[3:0] are ignored, ADDR[1:0] always read 0.)
Condition: {PFM_DATA_MSB==255}
Single Write (64-bits)
Address identifies the DWord to write. (ADDR[2:0] always read as 0.)
Quad Write (256-bits)
Address identifies the Quad DWord to write. (ADDR[4:3] are ignored, ADR[2:0] always read 0.)
Note: This field can only be modified when BUSY=0.
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