31.5.25 HSM Write Protection Control REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | HSMWPCTRL |
| Offset: | 0xb4 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WPLCK | WPEN | ||||||||
| Access | R/S | R/W | |||||||
| Reset | 0 | 0 |
Bits 31:8 – WPKEY[23:0] Writing a value other than FCW_WPCTRL_KEY to this field cancels the write operation this register and generates a bus error. This field always returns 0 on read.
Bit 1 – WPLCK WPCTRL Write LOCK
| Value | Name | Description |
|---|---|---|
| 1 | LOCKED | HSMWPCTRL register is write protected. This bit can only be cleared by a hardware reset. |
| 0 | UNLOCKED | HSMWPCTRL is not write protected. |
Bit 0 – WPEN Write Protection Enable
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | Register write protection enabled for HSM accesses for all registers (not just those prefixed with HSM) with the Write-Protected property. |
| 0 | DISABLE | Register write protection disabled for HSM accesses. |