31.5.7 Interrupt Flag Set REGISTER
- The interrupt flag bits of this register are set by hardware only.
- Interrupt flags must be cleared and then read back to confirm the clear before exiting the ISR to avoid double interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAGSET |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | R/S |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WRERR | RSTERR | HTDPGM | |||||||
| Access | R/S/HS | R/S/HS | R/S/HS | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECERR | OPERR | WPERR | BUSERR | FIFOERR | CFGERR | KEYERR | DONE | ||
| Access | R/S/HS | R/S/HS | R/S/HS | R/S/HS | R/S/HS | R/S/HS | R/S/HS | R/S/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 13 – WRERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 12 – RSTERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 8 – HTDPGM Read value reflects state of INTFLAG. Write value:
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 7 – SECERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 6 – OPERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 5 – WPERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 4 – BUSERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 3 – FIFOERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 2 – CFGERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 1 – KEYERR Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |
Bit 0 – DONE Read value reflects state of INTFLAG. Write value:
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will set the interrupt pending.
| Value | Name | Description |
|---|---|---|
| 1 | Set Interrupt Pending | |
| 0 | No effect |