31.5.12 Flash Write Data n REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DATA |
| Offset: | 0x2C + n*0x04 [n=0..7] |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATA[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DATA[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – DATA[31:0] The value in this register(s) is written to flash at the address defined in ADDR when a Write operation is commanded. Condition: {PFM_DATA_MSB==63} Double Write (64-bit data) Writes DATA0 to ADDR[31:3] with ADDR[2:0]=000 Writes DATA1 to ADDR[31:3] with ADDR[2:0]=100 Condition: {PFM_DATA_MSB==127} Single Write (32-bit data) Writes DATA0 to ADDR[31:2] with ADDR[1:0]=00 Quad Write (128-bit data) Writes DATA0 to ADDR[31:4], with ADDR[3:0]=0000 Writes DATA1 to ADDR[31:4], with ADDR[3:0]=0100 Writes DATA2 to ADDR[31:4], with ADDR[3:0]=1000 Writes DATA3 to ADDR[31:4], with ADDR[3:0]=1100 Condition: {PFM_DATA_MSB==255} Single Write (64-bit data) Writes DATA0 to ADDR]31:3], with ADDR[2:0]=000 Writes DATA1 to ADDR[31:3], with ADDR[2:0]=100 Quad Write (256-bit data) Writes DATA0 to ADDR[31:5], with ADDR[4:0]=0_0000 Writes DATA1 to ADDR[31:5], with ADDR[4:0]=0_0100 Writes DATA2 to ADDR[31:5], with ADDR[4:0]=0_1000 Writes DATA3 to ADDR[31:5], with ADDR[4:0]=0_1100 Writes DATA4 to ADDR[31:5], with ADDR[4:0]=1_0000 Writes DATA5 to ADDR[31:5], with ADDR[4:0]=1_0100 Writes DATA6 to ADDR[31:5], with ADDR[4:0]=1_1000 Writes DATA7 to ADDR[31:5], with ADDR[4:0]=1_1100 Note: This field can only be modified when BUSY=0.
The value in this register(s) is written to flash when a Write operation is commanded.
Single Write: (32-bit data)
Writes DATA0 to ADDR[31:2] with address bits [1:0] = 00
Quad Write: (128-bit data)
Writes DATA0 to ADDR[31:4], with address bits[3:0] = 0000
Writes DATA1 to ADDR[31:4], with address bits[3:0] = 0100
Writes DATA2 to ADDR[31:4], with address bits[3:0] = 1000
Writes DATA3 to ADDR[31:4], with address bits[3:0] = 1100
Note: This field can only be modified
when STATUS.BUSY=0.