22.6.5 CCP9 Control 2 High Register
- OCFEN through OCBEN (bits[13:9]) are implemented in the MCCP9 module only.
| Name: | CCP9CON2H |
| Offset: | 0xA76 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OENSYNC | OCFEN | OCEEN | OCDEN | OCCEN | OCBEN | OCAEN | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ICGSM[1:0] | AUXOUT[1:0] | ICS[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – OENSYNC Output Enable Synchronization bit
| Value | Description |
|---|---|
1 |
Update by output enable bits occurs on the next Time Base Reset or rollover |
0 |
Update by output enable bits occurs immediately |
Bit 13 – OCFEN Output Enable/Steering Control bit(1)
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bit 12 – OCEEN Output Enable/Steering Control bit(1)
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bit 11 – OCDEN Output Enable/Steering Control bit(1)
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bit 10 – OCCEN Output Enable/Steering Control bit(1)
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bit 9 – OCBEN Output Enable/Steering Control bit(1)
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bit 8 – OCAEN Output Enable/Steering Control bit
| Value | Description |
|---|---|
1 |
OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal |
0 |
OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin |
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
One-Shot mode: Falling edge from gating source disables future capture events
(ICDIS = |
01 |
One-Shot mode: Rising edge from gating source enables future capture events
(ICDIS = |
00 |
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will disable future capture events |
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
| Value | Description |
|---|---|
11 |
Input capture or output compare event; no signal in Timer mode |
10 |
Signal output is defined by module operating mode (see Auxiliary Output) |
01 |
Time base rollover event (all modes) |
00 |
Disabled |
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
| Value | Description |
|---|---|
111 |
CLC4 Output |
110 |
CLC3 Output |
101 |
CLC2 Output |
100 |
CLC1 Output |
011 |
Comparator 3 |
010 |
Comparator 2 |
001 |
Comparator 1 |
000 |
SCCP Input Capture x (ICx) pin (PPS) |