22.6.8 CCP9 Control 3 High Register
- These bits are implemented in the MCCP9 module only.
| Name: | CCP9CON3H |
| Offset: | 0xA7A |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OETRIG | OSCNT[2:0] | OUTM[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| POLACE | POLBDF | PSSACE[1:0] | PSSBDF[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – OETRIG CCPx Dead-Time Select bit
| Value | Description |
|---|---|
1 |
For Triggered mode (TRIGEN = |
0 |
Normal output pin operation |
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
| Value | Description |
|---|---|
111 |
Extends one-shot event by 7 time base periods (8 time base periods total) |
110 |
Extends one-shot event by 6 time base periods (7 time base periods total) |
101 |
Extends one-shot event by 5 time base periods (6 time base periods total) |
100 |
Extends one-shot event by 4 time base periods (5 time base periods total) |
011 |
Extends one-shot event by 3 time base periods (4 time base periods total) |
010 |
Extends one-shot event by 2 time base periods (3 time base periods total) |
001 |
Extends one-shot event by 1 time base period (2 time base periods total) |
000 |
Does not extend one-shot trigger event |
Bits 10:8 – OUTM[2:0] PWMx Output Mode Control bits(1)
| Value | Description |
|---|---|
| 111 | Reserved |
| 110 | Output Scan mode |
| 101 | Brush DC Output mode, forward |
| 100 | Brush DC Output mode, reverse |
| 011 | Reserved |
| 010 | Half-Bridge Output mode |
| 001 | Push-Pull Output mode |
| 000 | Steerable Single Output mode |
Bit 5 – POLACE CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit
| Value | Description |
|---|---|
| 1 |
Output pin polarity is active-low |
| 0 |
Output pin polarity is active-high |
Bit 4 – POLBDF CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit(1)
| Value | Description |
|---|---|
| 1 |
Output pin polarity is active-low |
| 0 |
Output pin polarity is active-high |
Bits 3:2 – PSSACE[1:0] PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits
| Value | Description |
|---|---|
11 |
Pins are driven active when a shutdown event occurs |
10 |
Pins are driven inactive when a shutdown event occurs |
0x |
Pins are in a High-Impedance state when a shutdown event occurs |
Bits 1:0 – PSSBDF[1:0] PWMx Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits(1)
| Value | Description |
|---|---|
11 |
Pins are driven active when a shutdown event occurs |
10 |
Pins are driven inactive when a shutdown event occurs |
0x |
Pins are in a High-Impedance state when a shutdown event occurs |