32.13 DFLL Electrical Specifications

Table 32-15. DFLL48M (Digital Frequency Locked Loop) Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDIO = AVDD = VDD 2.7V to 3.63V (unless otherwise stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temp
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
DFLL48 MHz (Closed Loop)^{(1,2 )}
DFLL_11	DFLL_CL_FIN^{(2 )}	DFLL Closed- Loop Input Frequency Range	0.732	32.768	33	kHz	—
Note: In Closed-Loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using the DFLLMUL register. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy. DFLLMUL = 1464, DFLLVAL.FINE = 512, DFLLCTRL.BPLCKC = 1: only fine value change, coarse value locked to the reset value. DFLLCTRL.QLDIS = 0: Quick lock enable, DFLLCTRL.CCDIS = 1: Enabling chill cycles might double the lock time. DFLLMUL.FSTEP = 10: Maximum fine step size, divided or dividing into two parts, search. 10 is a optimum value.