1.5.4.4.5 Reference Clock Input Pins

The input pins XCVR_REFCLK_P/N are assigned through the Libero transceiver configurator based on the targeted transceiver quad. The pins are identified based on quad. For example, where there are three transmit PLLs:

  • XCVR_#A_REFCLK_P/N—This REFCLK input is associated with the connection dedicated to the TXPLL_SSC. Also, this input has connectivity to the Global clock resource.
  • XCVR_#B_REFCLK_P/N
  • XCVR_#C_REFCLK_P/N (This input is only available in a subset of transceiver quads per device as shown in Figure   3 and Figure   4)

The following figure shows REFCLK input pins. These pins drive into the reference clock interface block to the TxPLLs and CDRs per quad or cascaded among several quads as required by the user design.

Figure 1-52. REFCLK Input Pin Diagram
Important: The XCVR_#[ABC]_REFCLK pins are available per quad. The REFCLK input to the reference clock interface (see Figure   1) connects the REFCLK source to the associated TxPLL.

The following figure shows the transceiver reference clock connectivity from the dedicated reference clock input pins to the cascaded clock routing to the TXPLLs.

Figure 1-53. Transceiver Reference Clock Interface
Important:
  • MPFS460 does not have Quad5.
  • XCVR_REF_CLK_A inputs to the quads have the greatest reach when cascading reference clocks to TXPLLs and XCVR Lanes.
  • See the device specific PPAT tables for die and package restrictions.

For more information on reference clock interface, see Transceiver Reference Clock Interface.