Compiling and running the profiled application

The second step is to compile the hardware and software, and then run the application on the board to collect the results. You can do this in the SmartHLS™ IDE by selecting RISC-V SoC Features > Reference SoC with HLS Accelerator(s) > Run software with Accelerators; or from the command-line using the following command.

shls soc_accel_proj_run

This will go through RTL generation, synthesis, place and route, FPGA programming, compiling software and running the application on the board. After this you should see the .prof files under hls_output/files on the host machine.

After the FPGA has been configured, and assuming there are no changes to the hardware, you can change the software part, compile it and rerun the executable without having to reprogram the FPGA. In the IDE, you can click the same Run software with accelerators button as above, skip the hardware part (i.e. compile software to hardware, generate SoC, place-and-route, program board etc), and run the software part (transform C++ source to invoke accelerator, and cross-compile software with accelerator drivers). You can also explicitly click the Cross-compile software with accelerator drivers button, and then Run software with accelerators (and skip all steps). Alternatively, from command-line, you could just run:

shls soc_sw_compile_accel
shls run_on_board

This will regenerate and copy again the *.prof files from the board to the host machine and visualize the results as described in the next section.