21.8.66 set_output_delay

Description

Defines the output delay of an output relative to a clock in the current scenario.

The set_output_delay command sets output path delays on output ports relative to a clock edge. Output ports have no output delay unless you specify it. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds output delay to path delay for paths ending at primary outputs.

Note:
  • The behavior of the -add_delay option is identical to that of PrimeTime(TM).
  • If, using the -add_delay mechanism, multiple constraints are otherwise identical, except they specify different -max or -min values.
    • the surviving -max constraint will be the maximum of the -max values.
    • the surviving -min constraint will be the minimum of the -min values.
set_output_delay [-max] [-min] delay_value -clock clock_ref [-clock_fall] [-rise] [-fall] \
[-add_delay] output_list

Arguments

ParameterTypeDescription
delay_valuefloatSpecifies the amount of time before a clock edge for which the signal is required. This represents a combinational path delay to a register outside the current design plus the library setup time (for maximum output delay) or hold time (for minimum output delay).
clockstringSpecifies the clock reference to which the specified output delay is related. This is a mandatory argument.
maxNoneSpecifies that delay_value refers to the longest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.
minNoneSpecifies that delay_value refers to the shortest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.
clock_fallNoneSpecifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.
riseNoneSpecifies that the delay is relative to a rising transition on the specified port(s). If -rise or -fall is not specified, then rising and falling delays are assumed to be equal.
fallNoneSpecifies that the delay is relative to a falling transition on the specified port(s). If -rise or -fall is not specified, then rising and falling delays are assumed to be equal.
add_delayNoneSpecifies that this output delay constraint should be added to an existing constraint on the same port(s). The -add_delay option is used to capture information on multiple paths with different clocks or clock edges leading to the same output port(s).
Note:
  • The behavior of the -add_delay option is identical to that of PrimeTime(TM).
  • If, using the -add_delay mechanism, multiple commands are otherwise identical, except they specify different -max or -min values.
  • the surviving -max constraint will be the maximum of the -max values.
  • the surviving -min constraint will be the minimum of the -min values.
output_listlist of stringProvides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).
Return TypeDescription
integerReturns the ID of the clock output delay constraint.

Error Codes

Error CodeDescription
Error: SDC0004Invalid output delay constraint: clk does not match any clock name or source.
Error: SDC0015Invalid output delay constraint: port list is incorrect.
Error: SDC0054Invalid I/O delay constraint: the min delay is greater than max delay.
Error: SDC0061Invalid output delay constraint: Missing or Illegal parameter/value.

Supported Families

PolarFire®
PolarFire SoC
SmartFusion® 2
IGLOO® 2
RTG4™

Example

The following example sets an output delay of 1.2 ns for port OUT1 relative to the rising edge of CLK1.

set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports OUT1]

The following example sets a different maximum and minimum output delay for port OUT1 relative to the falling edge of CLK2.

set_output_delay -min {OUT1} 1.0 -clock_fall -clock CLK2
set_output_delay -max {OUT1} 1.4 -clock_fall -clock CLK2

The following example demonstrates an override condition of two constraints. The first constraint is overridden because the second constraint specifies a different clock for the same output.

set_output_delay 1.0 {OUT1} -clock CLK1 -max
set_output_delay 1.4 {OUT1} -clock CLK2 -max

The next example is almost the same as the previous one, however, in this case, the user has specified -add_delay, so both constraints will be honored.

set_output_delay 1.0 {OUT1} -clock CLK1 –max
set_output_delay 1.4 {OUT1} -add_delay -clock CLK2 -max
The following example is more complex:
  • All constraints are for an output to port PAD1 relative to a rising edge clock CLK2. Each combination of {-rise, -fall} x {-max, -min} generates an independent constraint. But the max rise delay of 5 and the max rise delay of 7 interfere with each other.
  • For a -max option, the maximum value overrides all lower values. Thus the first constraint will be overridden and the max rise delay of 7 will survive.
set_output_delay 5 [get_clocks CLK2] [get_ports PAD1] -max -rise -add_delay # will be overridden
set_output_delay 3 [get_clocks CLK2] [get_ports PAD1] -min -fall -add_delay
set_output_delay 3 [get_clocks CLK2] [get_ports PAD1] -max -fall -add_delay
set_output_delay 7 [get_clocks CLK2] [get_ports PAD1] -max -rise -add_delay

Related Examples on GitHub

See Also