21.8.53 set_clock_to_output
(Ask a Question)Description
Defines the timing budget available inside the FPGA for an output relative to a clock.
This non-standard sdc command is intended to constrain an output FF clock-to-output time. Timing analysis is performed from the initial clock source. This non-standard sdc constraint is honored only by Libero SoC Place and Route and timing analysis. This command is not honored by Synplify synthesis or any other sdc-compliant synthesis tool. If sdc-compliant commands are desired, see set_max_delay, set_min_delay, and set_output_delay.
The clock argument for this command must be set to the actual clock driving the output FF.
set_clock_to_output delay_value -clock clock_ref [–max] [–min] output_listArguments
| Parameter | Type | Description |
|---|---|---|
delay_value | integer | Specifies the clock to output delay in nanoseconds. This time represents the amount of time available inside the FPGA between the launch clock edge and the data change at the output port. |
clock | string | Specifies the
clock
to which the specified clock to output is related. This is a
mandatory argument. Note: The clock parameter
needs to be set to the clock driving the
FF.
If it is a generated clock, STA is performed from the initial
clock source. |
max | None | Specifies that delay_value refers to the maximum clock to output at the specified output. If
you do not specify –max or –min
options, the tool assumes maximum and minimum clock to output
constraint values to be equal. |
min | None | Specifies that delay_value refers to the minimum clock to output at the specified output. If
you do not specify –max or –min
options, the tool assumes maximum and minimum clock to output
constraint values to be equal. |
output_list | list of strings | Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}). |
Error Codes
| Error Code | Description |
|---|---|
| None | Required parameter -clock is missing |
Supported Families
| PolarFire® |
| PolarFire SoC |
| SmartFusion® 2 |
| IGLOO® 2 |
| RTG4™ |
Examples
The following example sets an output delay of 0.3 ns for port Q relative to the clk clock.
set_clock_to_output -max 0.3 -clock { clk } [ get_ports { Q } ]The following example sets an output delay of 12 ns for port Q relative to the FCCC_C0_0/FCCC_C0_0/GL0 clock. Timing analysis will be performed from the CLK0_PAD clock source, assuming that there is a “create_clock” on CLK0_PAD and a “create_generated_clock” on FCCC_C0_0/FCCC_C0_0/GL0 whose source is defined as the CCC reference clock CLK0_PAD. It is recommended to use the supplied SDC constraints generated with the configured CCC core. The supplied SDC constraints can be added to the top-level design using the Derive Constraints action in the Libero SoC Constraints Manager or using the Derive Constraints utility described in the Custom Flow User Guide
set_clock_to_output -max 12 -clock { FCCC_C0_0/FCCC_C0_0/GL0 } [ get_ports { Q } ]