21.8.51 set_clock_groups
(Ask a Question)Description
Disables timing analysis between the specified clock groups. No paths are reported between the clock groups in both directions. Paths between clocks in the same group continue to be reported.
Note: If you use the same name and the same exclusive flag of a previously defined clock group to create a new clock group, the previous clock group is removed and a new one is created in its place. The exclusive flags for the arguments above are all mutually exclusive. Only one can be specified.
set_clock_groups [-name name ] \
[-physically exclusive | -logically exclusive | -asynchronous] \
[-comment comment_string ] \
-group clock_listArguments
| Parameter | Type | Description |
|---|---|---|
name | string | Name given to the clock group. |
physically_exclusive | None | Specifies that the clock groups are physically exclusive with respect to each other. Examples are multiple clocks feeding a register clock pin. The exclusive flags are all mutually exclusive. Only one can be specified. |
logically_exclusive | None | Specifies that the clocks groups are logically exclusive with respect to each other. Examples are clocks passing through a mux. |
asynchronous | None | Specifies that the clock groups are asynchronous with respect to each other, as there is no phase relationship between them. Note: The exclusive flags are all mutually exclusive. Only one can be specified. |
group | list of strings | Specifies a list of clocks. There can any number of groups specified in the set_clock_groups command. |
| Return Type | Description |
|---|---|
integer | Returns the ID of the clock group. |
Error Codes
| Error Code | Description |
|---|---|
| None | Invalid set_clock_groups constraint - only one of -physically_exclusive, -logically_exclusive or -asynchronous should be used. |
Supported Families
| PolarFire® |
| PolarFire SoC |
| SmartFusion® 2 |
| IGLOO® 2 |
| RTG4™ |
Example
- The
following figure
shows
how to use the set_clock_groups constraint for multiplexed
clocks..
SDC:
create_clock -name clk_1 -period 5 [ get_ports clk_1 ] create_clock -name clk_2 -period 10 [ get_ports clk_2 ] set_clock_groups -logically_exclusive -group clk_1 -group clk_2 - Here, there are three synchronous clocks receiving data from an asynchronous clock.
SDC:
create_clock -name clk_in -period 10 [ get_ports clk_in ] create_clock -name clk_50 -period 20 [ get_ports clk_50 ] create_generated_clock -name ccc_100 -divide_by 2 \ -source [ get_pins ccc_100_0/ccc_100_0/pll_inst_0/REF_CLK_0 ] \ [ get_pins ccc_100_0/ccc_100_0/pll_inst_0/OUT0 ] \ create_generated_clock -name clk_out -divide_by 1 \ -source [ get_pins { ccc_100_0/ccc_100_0/pll_inst_0/OUT0 } ] \ [ get_ports clk_out ] set_clock_groups -asynchronous -group { clk_in ccc_100 clk_out } -group clk_50