1.3.6 Clocking Pins

CCC blocks, located at each corner of the PolarFire SoC FPGAs, contain two PLLs and two DLLs that provide flexible on-chip and off-chip clock management and synthesis capabilities. CCCs are labeled according to their locations in the core. For example, the CCC located in the northeast corner is labeled as CCC_NE. For more information about clocking pins, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide.

Preferred clock inputs (CLKIN) are located on three sides of the device, with eight preferred clock inputs on the west side, twelve on the north side, and either 12 or 16 inputs on the south side, depending on the package. For more information about clocking pin names, descriptions, and operating voltages, see Table 1-3