1.3.1 User I/O

PolarFire SoC FPGA I/Os are paired up to meet the differential I/O standards and grouped into lanes of 12 buffers with a lane controller for memory interfaces. For more information about the memory controller, see PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.

There are two types of I/O buffers—HSIO and GPIO. HSIO is optimized for 1.2 Gbps (DDR4) operation with operating supplies between 1.1V and 1.8V. GPIO buffers support a wider range of I/O interfaces with speeds of up to 1066 Mbps when using single-ended standards and 1.25 Gbps when using differential standards, and operating supplies ranging from 1.2V to 3.3V. GPIO supports multiple standards, including 3.3V with an integrated Clock Data Recovery (CDR) to high-speed serial interfaces such as 1 GbE.

Each PolarFire SoC FPGA user I/O uses a IOxyBz naming convention, where:

• IO = The type of I/O.
• x = The I/O pair number in Bank z.
• y = P (positive) or N (negative). In Single-Ended mode, the I/O pair operates as two separate I/O—P and N. Differential mode is implemented with a fixed I/O pair and cannot be split with an adjacent I/O.
• B = Bank (see note in Supported I/O Features.
• z = Bank number.

  GPIOxyBz and HSIOxyBz are bi-directional user I/O pins that are capable of differential signaling.