37.13.9 ADCDSTAT1 – ADC Data Ready Status Register 1
This register contains the interrupt status of the individual analog input conversions. Each bit represents the data-ready status for its associated conversion result.
| Name: | ADCDSTAT1 |
| Offset: | 0xC0 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ARDY22 | ARDY21 | ARDY20 | ARDY19 | ARDY18 | ARDY17 | ARDY16 | |||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ARDY15 | ARDY14 | ARDY13 | ARDY12 | ARDY11 | ARDY10 | ARDY9 | ARDY8 | ||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ARDY7 | ARDY6 | ARDY5 | ARDY4 | ARDY3 | ARDY2 | ARDY1 | ARDY0 | ||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – ARDY Conversion Data Ready for Corresponding Analog Input Ready bits
| Value | Description |
|---|---|
| 1 | This bit is set when converted data is ready in the data register |
| 0 | This bit is cleared when the associated data register is read |