37.13.9 ADCDSTAT1 – ADC Data Ready Status Register 1

This register contains the interrupt status of the individual analog input conversions. Each bit represents the data-ready status for its associated conversion result.

Name: ADCDSTAT1
Offset: 0xC0
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  ARDY22ARDY21ARDY20ARDY19ARDY18ARDY17ARDY16 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 0000000 
Bit 15141312111098 
 ARDY15ARDY14ARDY13ARDY12ARDY11ARDY10ARDY9ARDY8 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 00000000 
Bit 76543210 
 ARDY7ARDY6ARDY5ARDY4ARDY3ARDY2ARDY1ARDY0 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – ARDY Conversion Data Ready for Corresponding Analog Input Ready bits

ValueDescription
1

This bit is set when converted data is ready in the data register

0

This bit is cleared when the associated data register is read