37.13.1 ADCCON1 – ADC Control Register 1

Integer

Fractional

12 bits (default)

10 bits

ADC core is disabled

ADC core is enabled

Do not freeze in the Debug mode

Freeze in the Debug mode

Continue module operation in the Idle mode

Discontinue module operation when device enters the Idle mode

When this bit is cleared, it forces the ADC Controller to engage the aforementioned synchronizers, except the situation, where ADCON3.ADCSEL == 2’b11, in which case the aforementioned synchronizers are always bypassed. When ADCON3.ADCSEL == 2’b11, the ADC control clock source is the DMA system clock itself, therefore the ADC control clock is a divided down synchronous version of the DMA system clock, situation which satisfies all the conditions to force FSYDMA high and bypass the ADC control clock domain to DMA system clock domain synchronizers.

When this bit is set, it forces the ADC Controller to bypass the internal double flip-flop synchronizers of the signals from the ADC control clock domain into the DMA system clock domain. It is essential that the user enables FSYDMA only if the DMA system clock is synchronous (edge-aligned) with the ADC control clock and the DMA system clock is faster than or same frequency with the ADC control clock.

Fast synchronous UPB clock is disabled

Fast synchronous UPB clock is enabled

When this bit is cleared, the scan cycle is re-triggerable, which means that if an edge-sensitive scan trigger arrives in the middle of a current scan cycle, the current conversion completes but the rest of the current scan is aborted, the EOS_RDY status bit is asserted and the scan cycle starts again from the beginning with the first channel included in the scan cycle.

By setting this bit, the user disallows the scan trigger to re-start the current scan cycle and the current scan cycle completes with its last included channel before getting re-started.

Shift x left 7 bit positions

Shift x left 6 bit positions

Shift x left 5 bit positions

Shift x left 4 bit positions

Scan trigger is positive edge sensitive. When the STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), only a single scan trigger is generated, which completes the scan of all selected analog inputs.

Scan trigger is high level sensitive. When the STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), the scan trigger continues for all selected analog inputs, until the STRIG option is removed.