37.13.24 ADCTRGSNS – ADC Trigger Level/Edge Sensitivity Register
This register contains the setting for trigger level for each ADC analog input.
| Name: | ADCTRGSNS |
| Offset: | 0x340 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1 | LVL0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – LVL Trigger Level and Edge Sensitivity bits
Note:
- This register specifies the trigger level for analog inputs 0 to 7.
- The higher analog input ID belongs to Class 3, and, therefore, is only scan triggered. All Class 3 analog inputs use the scan trigger, for which the level/edge is defined by the STRGLVL bit (ADCCON1[3]).
| Value | Description |
|---|---|
| 1 | Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high) |
| 0 | Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) |