37.13.7 ADCGIRQEN1 – ADC Global Interrupt Enable Register 1
This register specifies which of the individual input conversion interrupts can generate the global ADC interrupt.
| Name: | ADCGIRQEN1 |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| AGIEN22 | AGIEN21 | AGIEN20 | AGIEN19 | AGIEN18 | AGIEN17 | AGIEN16 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AGIEN15 | AGIEN14 | AGIEN13 | AGIEN12 | AGIEN11 | AGIEN10 | AGIEN9 | AGIEN8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AGIEN7 | AGIEN6 | AGIEN5 | AGIEN4 | AGIEN3 | AGIEN2 | AGIEN1 | AGIEN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – AGIEN ADC Global Interrupt Enable bits
| Value | Description |
|---|---|
| 1 | Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (‘x’ = 8-1) of the ADCDSTAT1 register) |
| 0 | Interrupts are disabled |